coreboot-kgpe-d16/src
Sridhar Siricilla 361e364635 soc/intel/common: Move CSE RW into new FMAP region to optimize boot time
CSE RW blob which will be used by coreboot to update CSE's RW partition,
is packed part of FW_MAIN_A and FW_MAIN_B. This will increase the size of
FW_MAIN_A and FW_MAIN_B. So, accordingly load and hash calculation of
FW_MAIN_A (or FW_MAIN_B) increases during verstage. It increases the boot
time by around 300ms.

The patch address the boot time by pulling CSE RW blob outside of
FW_MAIN_A and FW_MAIN_B. So, it creates new FMAP region within
RW_SECTION_A and RW_SECTION_B and adds CSE RW blob in the new regions
(ME_RW_A and ME_RW_B) as a CBFS file.

Boot Time Measurement details when CSE RW blob is added in the
ME_RW_A and ME_RW_B.
 --------------------------------------------------------
| Platform |   Old Boot Time      |   New Boot Time      |
 --------------------------------------------------------
| JSL      |  1.3s                |   1.06s              |
 --------------------------------------------------------
| TGL      |  1.63s               |   1.36s              |
 --------------------------------------------------------

Changes:
 1. Makefile change to accommodate CSE RW blob into  ME_RW_A/ME_RW_B
 2. Kconfig change to define CBFS name and default file name for RW blob
    metadata.
 3. CSE Lite Driver

BUG=b:169077783
TEST=Verified on JSL & TGL platforms

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If043c9cb99fb822b62633591bf9c5bd75dfe8349
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-18 01:26:44 +00:00
..
acpi acpigen: Add more useful helper functions 2020-11-09 07:30:01 +00:00
arch Revert "arch|cpu/x86: Add Kconfig option for x86 reset vector" 2020-11-17 07:46:34 +00:00
commonlib commonlib: Add timestamp values for forced delays 2020-11-16 11:01:37 +00:00
console console: Override uart base address 2020-11-09 07:46:10 +00:00
cpu Revert "arch|cpu/x86: Add Kconfig option for x86 reset vector" 2020-11-17 07:46:34 +00:00
device device/pci: Add NULL check for PCI driver's .ops 2020-11-16 12:15:38 +00:00
drivers src: Add missing 'include <console/console.h>' 2020-11-17 09:01:14 +00:00
ec src: Update some incorrect config options in comments 2020-11-16 12:09:58 +00:00
include src: Update some incorrect config options in comments 2020-11-16 12:09:58 +00:00
lib src: Add missing 'include <console/console.h>' 2020-11-17 09:01:14 +00:00
mainboard mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update 2020-11-18 01:26:37 +00:00
northbridge nb/intel/sandybridge: Clarify some parts of raminit 2020-11-16 12:07:20 +00:00
security src: Add missing 'include <console/console.h>' 2020-11-17 09:01:14 +00:00
soc soc/intel/common: Move CSE RW into new FMAP region to optimize boot time 2020-11-18 01:26:44 +00:00
southbridge src: Add missing 'include <console/console.h>' 2020-11-17 09:01:14 +00:00
superio superio/nuvoton: Factor out equivalent Kconfig option 2020-10-19 07:06:20 +00:00
vendorcode vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW45 FSP Memory map HOB mismatch 2020-11-16 11:03:00 +00:00
Kconfig soc/intel/xeon_sp: Move function debug macros 2020-10-29 16:44:19 +00:00