Patrick Georgi 1da104647d Get rid of AUTO_XIP_ROM_BASE ... That value is now generated from a code address and CONFIG_XIP_ROM_SIZE. This works as MTRRs are fully specified by their size and any address within the range. Change-Id: Id35d34eaf3be37f59cd2a968e3327d333ba71a34 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/348 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>		2011-10-28 22:17:10 +02:00
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bist.h	We call this cache as ram everywhere, so let's call it the same in Kconfig	2010-08-30 17:53:13 +00:00
cache.h	AMD Fam10 code breaks with gcc 4.5.0.	2010-09-17 21:38:40 +00:00
lapic.h	drop unneeded __ROMCC__ checks when the check for __PRE_RAM__ is more	2010-03-28 21:26:54 +00:00
lapic_def.h	- Renamed cpu header files	2004-10-14 20:13:01 +00:00
msr.h	AMD Fam10 code breaks with gcc 4.5.0.	2010-09-17 21:38:40 +00:00
mtrr.h	Get rid of AUTO_XIP_ROM_BASE	2011-10-28 22:17:10 +02:00
multiboot.h	Generate multiboot tables from coreboot tables.	2010-09-13 14:47:22 +00:00
name.h	Factor out fill_processor_name() and strcpy() functions.	2010-09-29 09:54:16 +00:00
pae.h	Since some people disapprove of white space cleanups mixed in regular commits	2010-04-27 06:56:47 +00:00
post_code.h	Unify use of post_code	2011-04-11 20:17:22 +00:00
smm.h	Make AMD SMM SMP aware	2011-07-13 02:01:35 +02:00
stack.h	Since some people disapprove of white space cleanups mixed in regular commits	2010-04-27 06:56:47 +00:00
tsc.h	drop unneeded __ROMCC__ checks when the check for __PRE_RAM__ is more	2010-03-28 21:26:54 +00:00