37231fb2fe
Prior to coreboot sending EOP messages during post, it's important to ensure that CSE is not in Idle state. In case CSE is in Dev Idle state (which means D0I3 bit is set), reset this bit before sending EOP command. This patch ensures coreboot has provision to send CSE EOP messages even after the FSP Notify phase without any delays waiting for the device to respond or timeout. BUG=b:200644229 TEST=Able to send CSE EOP message even after FSP Notify phase. Attempting CSE EOP msg sending post FSP notify without this code change causes `timeout` issue as below: BS: BS_PAYLOAD_LOAD exit times (exec / console): 171 / 0 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post HECI: timed out reading answer! HECI: Failed to receive! HECI: receive Failed HECI: EOP send/receive fail ERROR: Failed to send EOP to CSE, 2 cse: CSE status registers: HFSTS1: 0x90000255, HFSTS2: 0xf10516 HFSTS3: 0x20 VB2:vb2api_fail() Need recovery, reason: 0x31 / 0xc Saving nvdata board_reset() called! full_reset() called! Attempting CSE EOP msg sending post FSP notify with this code change is `successful` as below: BS: BS_PAYLOAD_LOAD exit times (exec / console): 170 / 0 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot Change-Id: Iae1bc52e94b08f97004424ea0c147d6da8aca6e2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> |
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| 3rdparty | ||
| Documentation | ||
| LICENSES | ||
| configs | ||
| payloads | ||
| spd | ||
| src | ||
| tests | ||
| util | ||
| .checkpatch.conf | ||
| .clang-format | ||
| .editorconfig | ||
| .gitignore | ||
| .gitmodules | ||
| .gitreview | ||
| AUTHORS | ||
| COPYING | ||
| MAINTAINERS | ||
| Makefile | ||
| Makefile.inc | ||
| README.md | ||
| gnat.adc | ||
| toolchain.inc | ||
README.md
coreboot README
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
Payloads
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
Supported Hardware
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
Build Requirements
- make
- gcc / g++
Because Linux distribution compilers tend to use lots of patches. coreboot
does lots of "unusual" things in its build system, some of which break due
to those patches, sometimes by gcc aborting, sometimes - and that's worse -
by generating broken object code.
Two options: use our toolchain (eg. make crosstools-i386) or enable the
ANY_TOOLCHAINKconfig option if you're feeling lucky (no support in this case). - iasl (for targets with ACPI support)
- pkg-config
- libssl-dev (openssl)
Optional:
- doxygen (for generating/viewing documentation)
- gdb (for better debugging facilities on some targets)
- ncurses (for
make menuconfigandmake nconfig) - flex and bison (for regenerating parsers)
Building coreboot
Please consult https://www.coreboot.org/Build_HOWTO for details.
Testing coreboot Without Modifying Your Hardware
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Website and Mailing List
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
Copyright and License
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.