3858fb121e
Found-by: Coverity CID 1429980 Change-Id: Ia72b9dbe029a5da98e408a9cf16fa4a93b10917a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
171 lines
6.7 KiB
C
171 lines
6.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpigen.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <fsp/util.h>
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#include <stdint.h>
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#include <soc/memmap.h>
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/*
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*
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* +--------------------------------+
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* | |
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* | |
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* | |
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* | |
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* | |
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* | |
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* | |
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* reserved_dram_end +--------------------------------+
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* | |
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* | verstage (if reqd) |
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* | (VERSTAGE_SIZE) |
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* +--------------------------------+ VERSTAGE_ADDR
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* | |
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* | FSP-M |
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* | (FSP_M_SIZE) |
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* +--------------------------------+ FSP_M_ADDR
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* | |X86_RESET_VECTOR = ROMSTAGE_ADDR + ROMSTAGE_SIZE - 0x10
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* | romstage |
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* | (ROMSTAGE_SIZE) |
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* +--------------------------------+ ROMSTAGE_ADDR
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* | bootblock |
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* | (C_ENV_BOOTBLOCK_SIZE) |
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* +--------------------------------+ BOOTBLOCK_ADDR
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* | Unused hole |
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* | (86KiB) |
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* +--------------------------------+
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* | FMAP cache (FMAP_SIZE) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
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* | Early Timestamp region (512B) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
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* | Preram CBMEM console |
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* | (PRERAM_CBMEM_CONSOLE_SIZE) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
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* | PSP shared (vboot workbuf) |
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* | (PSP_SHAREDMEM_SIZE) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE
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* | APOB (64KiB) |
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* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
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* | Early BSP stack |
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* | (EARLYRAM_BSP_STACK_SIZE) |
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* reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
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* | DRAM |
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* +--------------------------------+ 0x100000
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* | Option ROM |
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* +--------------------------------+ 0xc0000
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* | Legacy VGA |
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* +--------------------------------+ 0xa0000
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* | DRAM |
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* +--------------------------------+ 0x0
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*/
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static void read_resources(struct device *dev)
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{
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uint32_t mem_usable = (uintptr_t)cbmem_top();
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unsigned int idx = 0;
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const struct hob_header *hob = fsp_get_hob_list();
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const struct hob_resource *res;
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uintptr_t early_reserved_dram_start, early_reserved_dram_end;
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const struct memmap_early_dram *e = memmap_get_early_dram_usage();
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early_reserved_dram_start = e->base;
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early_reserved_dram_end = e->base + e->size;
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/* 0x0 - 0x9ffff */
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ram_resource(dev, idx++, 0, 0xa0000 / KiB);
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/* 0xa0000 - 0xbffff: legacy VGA */
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mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
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/* 0xc0000 - 0xfffff: Option ROM */
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reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
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/* 1MB - bottom of DRAM reserved for early coreboot usage */
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ram_resource(dev, idx++, (1 * MiB) / KiB,
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(early_reserved_dram_start - (1 * MiB)) / KiB);
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/* DRAM reserved for early coreboot usage */
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reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB,
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(early_reserved_dram_end - early_reserved_dram_start) / KiB);
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/* top of DRAM consumed early - low top usable RAM
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* cbmem_top() accounts for low UMA and TSEG if they are used. */
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ram_resource(dev, idx++, early_reserved_dram_end / KiB,
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(mem_usable - early_reserved_dram_end) / KiB);
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mmconf_resource(dev, MMIO_CONF_BASE);
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if (!hob) {
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printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n",
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__func__);
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return;
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}
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for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) {
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if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR)
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continue;
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res = fsp_hob_header_to_resource(hob);
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if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && res->addr < mem_usable)
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continue; /* 0 through low usable was set above */
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if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO)
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continue; /* Done separately */
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if (res->type == EFI_RESOURCE_SYSTEM_MEMORY)
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ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
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else if (res->type == EFI_RESOURCE_MEMORY_RESERVED)
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reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
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else
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printk(BIOS_ERR, "Error: failed to set resources for type %d\n",
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res->type);
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}
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}
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/* Used by \_SB.PCI0._CRS */
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static void root_complex_fill_ssdt(const struct device *device)
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{
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msr_t msr;
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if (!device) {
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printk(BIOS_ERR, "%s: device is NULL! ACPI SSDT will be incomplete.\n",
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__func__);
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return;
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}
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acpigen_write_scope(acpi_device_scope(device));
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msr = rdmsr(TOP_MEM);
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acpigen_write_name_dword("TOM1", msr.lo);
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msr = rdmsr(TOP_MEM2);
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/*
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* Since XP only implements parts of ACPI 2.0, we can't use a qword
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* here.
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* See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
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* slide 22ff.
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* Shift value right by 20 bit to make it fit into 32bit,
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* giving us 1MB granularity and a limit of almost 4Exabyte of memory.
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*/
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acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
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acpigen_pop_len();
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}
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static struct device_operations root_complex_operations = {
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.read_resources = read_resources,
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.enable_resources = pci_dev_enable_resources,
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.acpi_fill_ssdt = root_complex_fill_ssdt,
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};
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static const struct pci_driver family17_root_complex __pci_driver = {
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.ops = &root_complex_operations,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB,
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};
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