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Subrata Banik 38abbdab71 soc/intel/common/../cse: Avoid caching of CSE BAR 
This patch ensures all attempts to read CSE BAR is performing PCI config
space read and returning the BAR value rather than using cached value.

This refactoring is useful to read BAR of all CSE devices rather than
just HECI 1 alone.

Additionally, change the return type of get_cse_bar() from `uintptr_t`
to `void *` to avoid typecasting while calling read32/write32 functions.

BUG=b:200644229
TEST=Able to build and boot ADLRVP where CSE is able to perform PCI
enumeration and send the EOP message at post.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Id4ecc9006d6323b7c9d7a6af1afa5cfe63d933e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 		2021-10-02 08:44:42 +00:00
3rdparty Update vboot submodule to upstream main (13f601f) 2021-09-29 15:35:28 +00:00
Documentation doc/mainboard/ocp: update Delta Lake documentation 2021-09-23 06:28:39 +00:00
LICENSES treewide: Remove trailing whitespace 2021-02-17 17:30:05 +00:00
configs configs/config.google_meep_cros: don't select ADD_FSP_BINARIES 2021-09-04 18:33:29 +00:00
payloads device/mmio: Make buffer_to_fifo32() take a const buffer 2021-09-20 12:07:51 +00:00
spd spd: Add SPD for 4JQA-0622AD to spd/ 2021-09-23 06:24:11 +00:00
src soc/intel/common/../cse: Avoid caching of CSE BAR 2021-10-02 08:44:42 +00:00
tests tests: Add lib/cbfs-lookup-test test case 2021-09-14 23:35:38 +00:00
util util/liveiso: Install nvme-cli tool 2021-10-01 15:08:07 +00:00
.checkpatch.conf
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.clang-format
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.editorconfig
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.gitignore
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.gitmodules .gitmodules: Update intel-microcode submodule to track branch=main 2021-06-09 17:20:50 +00:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
AUTHORS
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COPYING
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MAINTAINERS MAINTAINERS: update lists for soc/intel/xeon_sp and mb/ocp/deltalake 2021-09-23 06:28:45 +00:00
Makefile util/kconfig: Uprev to Linux 5.13's kconfig 2021-07-13 20:28:14 +00:00
Makefile.inc build system: Deduplicate symbols in objdump 2021-07-23 15:06:56 +00:00
README.md
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gnat.adc
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toolchain.inc toolchain.inc: copy architecture specific CFLAGS to GCC_ADAFLAGS 2021-07-01 09:43:54 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.