f836a234e2
On the Picasso architecture, the PSP is responsible for setting up DRAM before releasing the x86. The APCB (AGESA PSP Configuration Block) contains multiple SPDs and the GPIO numbers used to select the correct SPD. Since the source to build the APCBs is not public, it can't be built as part of the coreboot build. To work around this problem, we use a template APCB and inject the relevant information. BUG=b:147042464 Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I88a09743f8e8a184c47071ee5e417f5b6bdb7467 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2123799 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> |
||
|---|---|---|
| .. | ||
| README | ||
| apcb_edit.py | ||
README
The necessary tools for building APCBs are not available for use by coreboot. This tool allows patching an existing APCB binary with specific SPDs and GPIO selection pins.