coreboot-kgpe-d16/src/northbridge/intel
Nico Huber 393619b9a6 intel/gm45: Add more debug output to read/write training
Add debug output for the timing values of the edges found during
read and write training.

Now, output for one DIMM of DDR3-1066 in a roda/rk9 looks like:

[...]
Lower bound for byte lane 0 on channel 0: 0.0
Upper bound for byte lane 0 on channel 0: 8.4
Final timings for byte lane 0 on channel 0: 4.2
Lower bound for byte lane 1 on channel 0: 0.0
Upper bound for byte lane 1 on channel 0: 10.2
Final timings for byte lane 1 on channel 0: 5.1
Lower bound for byte lane 2 on channel 0: 0.0
Upper bound for byte lane 2 on channel 0: 7.5
Final timings for byte lane 2 on channel 0: 3.6
Lower bound for byte lane 3 on channel 0: 0.0
Upper bound for byte lane 3 on channel 0: 11.4
Final timings for byte lane 3 on channel 0: 5.6
Lower bound for byte lane 4 on channel 0: 0.0
Upper bound for byte lane 4 on channel 0: 9.4
Final timings for byte lane 4 on channel 0: 4.6
Lower bound for byte lane 5 on channel 0: 0.0
Upper bound for byte lane 5 on channel 0: 11.2
Final timings for byte lane 5 on channel 0: 5.5
Lower bound for byte lane 6 on channel 0: 0.0
Upper bound for byte lane 6 on channel 0: 8.4
Final timings for byte lane 6 on channel 0: 4.2
Lower bound for byte lane 7 on channel 0: 0.0
Upper bound for byte lane 7 on channel 0: 10.4
Final timings for byte lane 7 on channel 0: 5.2
Lower bound for group 0 on channel 0: 1.7.5
Upper bound for group 0 on channel 0: 2.2.2
Final timings for group 0 on channel 0: 1.10.7
Lower bound for group 1 on channel 0: 1.6.1
Upper bound for group 1 on channel 0: 2.0.2
Final timings for group 1 on channel 0: 1.9.1
Lower bound for group 2 on channel 0: 2.0.7
Upper bound for group 2 on channel 0: 2.8.1
Final timings for group 2 on channel 0: 2.4.4
Lower bound for group 3 on channel 0: 2.4.7
Upper bound for group 3 on channel 0: 3.0.0
Final timings for group 3 on channel 0: 2.8.3
[...]

Final timings are always the average of the two bounds. The last dots
separate eights (not decimals) and the middles are elenvenths or twelfths
depending on the clock speed (twelfths in this case).

Change-Id: Idb7c84b514716c7265b94890c39b7225de7800dc
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3257
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:07:22 +02:00
..
e7501 Drop prototype guarding for romcc 2013-05-10 00:06:46 +02:00
e7505 x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
e7520 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
e7525 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
gm45 intel/gm45: Add more debug output to read/write training 2013-05-22 18:07:22 +02:00
haswell haswell: use tsc for udelay() 2013-05-07 18:32:41 +02:00
i440bx x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
i440lx GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
i855 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
i945 Intel i945: ACPI: Add _OSC method 2013-04-18 02:48:02 +02:00
i3100 Get rid of a number of __GNUC__ checks 2013-05-10 17:31:31 +02:00
i5000 intel/i5000: Remove unused copy of udelay.c 2013-05-21 17:46:02 +02:00
i82810 x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
i82830 x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
sandybridge boot: remove cbmem_post_handling() 2013-05-01 07:11:22 +02:00
sch x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
Kconfig haswell: Add initial support for Haswell platforms 2013-03-14 01:44:40 +01:00
Makefile.inc haswell: Add initial support for Haswell platforms 2013-03-14 01:44:40 +01:00