399fcdd40d
Southbridge SP5100 support was compiled with SB700 code, but static device info structure would use sp5100/chip.h. To solve this drop support for separate chip sp5100 and adjust the relevant Kconfig options. Removes chip directory: src/southbridge/amd/sp5100/ Rename Kconfig option from: SOUTHBRIDGE_AMD_SP5100 to: SOUTHBRIDGE_AMD_SUBTYPE_SP5100 Change-Id: I873c6ad3624ee69165da6ab7287dfb7e006ee8e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/679 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
139 lines
4.8 KiB
Text
139 lines
4.8 KiB
Text
# GPP1 (dev2,3) --> slot 7
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# GPP2 (dev12) --> slot 6
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# GPP3A (dev9,A) --> Lan1, Lan2
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# sample config for supermicro/h8scm_fam10
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chip northbridge/amd/amdfam10/root_complex
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device lapic_cluster 0 on
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chip cpu/amd/socket_C32 #L1 and DDR3
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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subsystemid 0x15d9 0x1511 inherit
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chip northbridge/amd/amdfam10
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##device pci 18.0 on end
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##device pci 18.0 on end
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device pci 18.0 on # northbridge
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chip southbridge/amd/sr5650
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device pci 0.0 on end # HT 0x9600
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device pci 0.1 on end # CLKCONFIG
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device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
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device pci 3.0 off end # PCIE P2P bridge 0x960b
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device pci 4.0 off end # PCIE P2P bridge 0x9604
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device pci 5.0 off end # PCIE P2P bridge 0x9605
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device pci 6.0 on end # PCIE P2P bridge 0x9606
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device pci 7.0 on end # PCIE P2P bridge 0x9607
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device pci 8.0 on end # NB/SB Link P2P bridge
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device pci 9.0 on end #
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device pci a.0 on end #
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device pci b.0 on end #
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device pci c.0 on end #
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device pci d.0 on end #
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register "gpp1_configuration" = "0" # Configuration 16:0 default
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register "gpp2_configuration" = "1" # Configuration 8:8
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#register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0
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register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1
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register "port_enable" = "0x1ffc"
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end
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chip southbridge/amd/sb700 # (model:sp5100) it is under NB/SB Link, but on the same pri bus
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device pci 11.0 on end # SATA
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device pci 12.0 on end # USB
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device pci 12.1 on end # USB
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device pci 12.2 on end # USB
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device pci 13.0 on end # USB
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device pci 13.1 on end # USB
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device pci 13.2 on end # USB
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device pci 14.0 on end # SM
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device pci 14.1 on end # IDE 0x439c
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device pci 14.2 off end # HDA 0x4383, h8scm doesnt have codec.
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device pci 14.3 on # LPC 0x439d
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chip superio/winbond/w83627hf
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 off # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off # SFI
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io 0x62 = 0x100
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end
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device pnp 2e.7 off # GPIO_GAME_MIDI
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io 0x60 = 0x220
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io 0x62 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.8 off end # WDTO_PLED
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device pnp 2e.9 off end # GPIO_SUSLED
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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irq 0x70 = 5
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end
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end #superio/winbond/w83627hf
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end #LPC
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device pci 14.4 on end # PCI 0x4384
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device pci 14.5 on end # USB 2
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register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
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end #southbridge/amd/sb700
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end # device pci 18.0
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 19.0 on end
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device pci 19.1 on end
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device pci 19.2 on end
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device pci 19.3 on end
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device pci 19.4 on end
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end
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end #pci_domain
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#for node 32 to node 63
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# device pci_domain 0 on
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# chip northbridge/amd/amdfam10
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# device pci 00.0 on end# northbridge
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# device pci 00.0 on end
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# device pci 00.0 on end
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# device pci 00.0 on end
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# device pci 00.1 on end
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# device pci 00.2 on end
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# device pci 00.3 on end
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# device pci 00.4 on end
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# device pci 00.5 on end
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# end
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# end #pci_domain
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# chip drivers/generic/debug
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# device pnp 0.0 off end # chip name
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# device pnp 0.1 on end # pci_regs_all
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# device pnp 0.2 off end # mem
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# device pnp 0.3 off end # cpuid
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# device pnp 0.4 off end # smbus_regs_all
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# device pnp 0.5 off end # dual core msr
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# device pnp 0.6 off end # cache size
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# device pnp 0.7 off end # tsc
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# device pnp 0.8 off end # hard reset
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# device pnp 0.9 off end # mcp55
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# device pnp 0.a on end # GH ext table
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# end
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end
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