3b0a626edc
The Intel Stargo2 is a communications device reference design. This mainboard uses the Sandy/Ivy Bridge and is paired with the i89xx southbridge. The FSP package is available from Intel: https://intel.com/fsp. Change-Id: I75c527f0eb0de1ee6ac13d8d276d7cf23b5b120c Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/12170 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
63 lines
1.6 KiB
C
63 lines
1.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2013 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <southbridge/intel/fsp_i89xx/nvs.h>
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#include <southbridge/intel/fsp_i89xx/pch.h>
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#include <southbridge/intel/fsp_i89xx/me.h>
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#include <northbridge/intel/fsp_sandybridge/sandybridge.h>
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#include <cpu/intel/fsp_model_206ax/model_206ax.h>
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void mainboard_smi_sleep(u8 slp_typ)
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{
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u8 reg8;
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switch (slp_typ) {
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case SLP_TYP_S3:
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case SLP_TYP_S4:
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case SLP_TYP_S5:
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break;
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}
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}
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static int mainboard_finalized = 0;
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int mainboard_smi_apmc(u8 apmc)
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{
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switch (apmc) {
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case APM_CNT_FINALIZE:
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if (mainboard_finalized) {
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printk(BIOS_DEBUG, "SMI#: Already finalized\n");
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return 0;
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}
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intel_me_finalize_smm();
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intel_pch_finalize_smm();
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intel_sandybridge_finalize_smm();
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intel_model_206ax_finalize_smm();
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mainboard_finalized = 1;
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break;
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}
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return 0;
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}
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