Aamir Bohra 3b1a42f95d mb/google/hatch: Enable LPC/eSPI controller ... Enable LPC/eSPI controller(D31:F0). EC would be using eSPI interface, since the strap GPP_C5 is pulled up. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Ia4baf80a775ba8898055f82e80dc583e65c4ed0b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>		2018-12-28 06:38:10 +00:00
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spd	mb/google/hatch: Add memory init setup for hatch	2018-12-23 05:12:14 +00:00
variants	mb/google/hatch: Enable LPC/eSPI controller	2018-12-28 06:38:10 +00:00
acpi_tables.c
board_info.txt
bootblock.c
chromeos.c	mb/google/hatch: Fixes to initial hatch mainboard checkin	2018-12-22 12:14:20 +00:00
chromeos.fmd	mb/google/hatch: Modify hatch SPI flash layout	2018-12-25 03:43:34 +00:00
dsdt.asl	mb/google/hatch: Add SoC and EC asl files in DSDT	2018-12-25 03:42:23 +00:00
Kconfig	mb/google/hatch: Enable EC LPC interface and configure IO decode range	2018-12-25 03:42:59 +00:00
Kconfig.name
Makefile.inc	mb/google/hatch: Add memory init setup for hatch	2018-12-23 05:12:14 +00:00
ramstage.c
romstage.c	mb/google/hatch: Add memory init setup for hatch	2018-12-23 05:12:14 +00:00
smihandler.c	mb/google/hatch: Add SMI handlers	2018-12-27 22:08:57 +00:00