ef6cb094b8
cause problems with certain toolchains. This patch will also safe some hard disk space for those of us working on laptops or netbooks with always too small disks. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
436 lines
12 KiB
Text
436 lines
12 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 AMD
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## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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##
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## Compute the location and size of where this firmware image
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## (coreboot plus bootloader) will live in the boot rom chip.
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##
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if USE_FAILOVER_IMAGE
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default ROM_SECTION_SIZE = FAILOVER_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
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else
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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end
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##
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## Compute the start location and size size of
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## The coreboot bootloader.
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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##
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## Compute where this copy of coreboot will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up coreboot,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=65536
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if USE_FAILOVER_IMAGE
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default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
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else
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if USE_FALLBACK_IMAGE
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default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
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else
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default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
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end
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end
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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#needed by irq_tables and mptable and acpi_tables
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object get_bus_conf.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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if HAVE_ACPI_TABLES
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object acpi_tables.o
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object fadt.o
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makerule dsdt.c
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depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
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action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
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action "mv dsdt_lb.hex dsdt.c"
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end
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object ./dsdt.o
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#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
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if ACPI_SSDTX_NUM
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makerule ssdt6.c
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depends "$(MAINBOARD)/dx/pci6.asl"
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action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci6.asl"
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action "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex"
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action "mv pci6.hex ssdt6.c"
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end
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object ./ssdt6.o
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makerule ssdt5.c
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depends "$(MAINBOARD)/dx/pci5.asl"
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action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci5.asl"
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action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
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action "mv pci5.hex ssdt5.c"
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end
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object ./ssdt5.o
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end
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end
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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makerule ./cache_as_ram_auto.o
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
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end
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else
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makerule ./cache_as_ram_auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
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action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
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end
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end
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end
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if USE_FAILOVER_IMAGE
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else
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if CONFIG_AP_CODE_IN_CAR
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makerule ./apc_auto.o
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depends "$(MAINBOARD)/apc_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
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end
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ldscript /arch/i386/init/ldscript_apc.lb
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end
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end
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##
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## Build our 16 bit and 32 bit coreboot entry code
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##
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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else
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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end
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##
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## Build our reset vector (This is where coreboot is entered)
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##
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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else
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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end
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit southbridge/nvidia/mcp55/id.inc
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ldscript /southbridge/nvidia/mcp55/id.lds
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##
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## ROMSTRAP table for MCP55
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##
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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mainboardinit southbridge/nvidia/mcp55/romstrap.inc
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ldscript /southbridge/nvidia/mcp55/romstrap.lds
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end
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else
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if USE_FALLBACK_IMAGE
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mainboardinit southbridge/nvidia/mcp55/romstrap.inc
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ldscript /southbridge/nvidia/mcp55/romstrap.lds
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end
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end
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if USE_DCACHE_RAM
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##
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## Setup Cache-As-Ram
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##
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mainboardinit cpu/amd/car/cache_as_ram.inc
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end
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###
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### This is the early phase of coreboot startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover_failover.lds
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end
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end
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else
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if USE_FALLBACK_IMAGE
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover.lds
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end
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end
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end
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##
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## Setup RAM
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##
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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initobject cache_as_ram_auto.o
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else
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mainboardinit ./cache_as_ram_auto.inc
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end
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end
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##
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## Include the secondary Configuration files
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##
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if CONFIG_CHIP_NAME
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config chip.h
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end
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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chip cpu/amd/socket_F
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8 #mc0
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device pci 18.0 on
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# devices on link 0, link 0 == LDT 0
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chip southbridge/nvidia/mcp55
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device pci 0.0 on end # HT
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device pci 1.0 on # LPC
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chip superio/winbond/w83627ehg
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off # SFI
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io 0x62 = 0x100
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end
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device pnp 2e.7 off # GPIO_GAME_MIDI
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io 0x60 = 0x220
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io 0x62 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.8 off end # WDTO_PLED
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device pnp 2e.9 off end # GPIO_SUSLED
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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irq 0x70 = 5
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end
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end
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end
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device pci 1.1 on # SM 0
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chip drivers/generic/generic #dimm 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic #dimm 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic #dimm 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic #dimm 0-1-1
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device i2c 53 on end
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end
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chip drivers/generic/generic #dimm 1-0-0
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device i2c 54 on end
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end
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chip drivers/generic/generic #dimm 1-0-1
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device i2c 55 on end
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end
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chip drivers/generic/generic #dimm 1-1-0
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device i2c 56 on end
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end
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chip drivers/generic/generic #dimm 1-1-1
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device i2c 57 on end
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end
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end # SM
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device pci 1.1 on # SM 1
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#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
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# chip drivers/generic/generic #PCIXA Slot1
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# device i2c 50 on end
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# end
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# chip drivers/generic/generic #PCIXB Slot1
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# device i2c 51 on end
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# end
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# chip drivers/generic/generic #PCIXB Slot2
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# device i2c 52 on end
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# end
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# chip drivers/generic/generic #PCI Slot1
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# device i2c 53 on end
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# end
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# chip drivers/generic/generic #Master MCP55 PCI-E
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# device i2c 54 on end
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# end
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# chip drivers/generic/generic #Slave MCP55 PCI-E
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# device i2c 55 on end
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# end
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chip drivers/generic/generic #MAC EEPROM
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device i2c 51 on end
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end
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end # SM
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device pci 2.0 on end # USB 1.1
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device pci 2.1 on end # USB 2
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device pci 4.0 on end # IDE
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device pci 5.0 on end # SATA 0
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device pci 5.1 on end # SATA 1
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device pci 5.2 on end # SATA 2
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device pci 6.0 on end # PCI
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device pci 6.1 on end # AZA
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device pci 8.0 on end # NIC
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device pci 9.0 on end # NIC
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device pci a.0 on end # PCI E 5
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device pci b.0 off end # PCI E 4
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device pci c.0 off end # PCI E 3
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device pci d.0 on end # PCI E 2
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device pci e.0 off end # PCI E 1
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device pci f.0 on end # PCI E 0
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register "ide0_enable" = "1"
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register "sata0_enable" = "1"
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register "sata1_enable" = "1"
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register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
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register "mac_eeprom_addr" = "0x51"
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end
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end # device pci 18.0
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device pci 18.0 on end # Link 1
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device pci 18.0 on
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# devices on link 2, link 2 == LDT 2
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chip southbridge/nvidia/mcp55
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device pci 0.0 on end # HT
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device pci 1.0 on end # LPC
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device pci 1.1 on end # SM 0
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device pci 2.0 off end # USB 1.1
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device pci 2.1 off end # USB 2
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device pci 4.0 off end # IDE
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device pci 5.0 on end # SATA 0
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device pci 5.1 on end # SATA 1
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device pci 5.2 on end # SATA 2
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device pci 6.0 off end # PCI
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device pci 6.1 off end # AZA
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device pci 8.0 on end # NIC
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device pci 9.0 on end # NIC
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device pci a.0 on end # PCI E 5
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device pci b.0 off end # PCI E 4
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device pci c.0 off end # PCI E 3
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device pci d.0 on end # PCI E 2
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device pci e.0 on end # PCI E 1
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device pci f.0 on end # PCI E 0
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register "ide0_enable" = "1"
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register "sata0_enable" = "1"
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register "sata1_enable" = "1"
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register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
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register "mac_eeprom_addr" = "0x51"
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end
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end # device pci 18.0
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end # mc0
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end # PCI domain
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# chip drivers/generic/debug
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# device pnp 0.0 off end # chip name
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# device pnp 0.1 on end # pci_regs_all
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# device pnp 0.2 on end # mem
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# device pnp 0.3 off end # cpuid
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# device pnp 0.4 on end # smbus_regs_all
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# device pnp 0.5 off end # dual core msr
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# device pnp 0.6 off end # cache size
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# device pnp 0.7 off end # tsc
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# device pnp 0.8 off end # io
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# device pnp 0.9 off end # io
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# end
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end #root_complex
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