3b618bbe31
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I57fc98788bb47df16d6aedd0f0701e9991801743 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
90 lines
2.8 KiB
Text
90 lines
2.8 KiB
Text
#
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# This file is part of the coreboot project.
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#
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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chip northbridge/amd/agesa/family15tn/root_complex
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device cpu_cluster 0 on
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chip cpu/amd/agesa/family15tn
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device lapic 10 on end
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end
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end
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device domain 0 on
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subsystemid 0x1022 0x1410 inherit
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chip northbridge/amd/agesa/family15tn
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device pci 0.0 on end # Root Complex
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device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
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device pci 1.1 on end # Internal Multimedia
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device pci 2.0 on end # PCIE SLOT0 x8
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device pci 3.0 off end
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device pci 4.0 on end # LAN
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device pci 5.0 on end # PCIE MINI0
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device pci 6.0 on end # PCIE MINI1
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device pci 7.0 off end
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device pci 8.0 off end # NB/SB Link P2P bridge
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end #chip northbridge/amd/agesa/family15tn
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chip southbridge/amd/agesa/hudson
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device pci 10.0 on end # XHCI HC0
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device pci 10.1 on end # XHCI HC1
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device pci 11.0 on end # SATA
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device pci 12.0 on end # USB
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device pci 12.2 on end # USB
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device pci 13.0 on end # USB
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device pci 13.2 on end # USB
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device pci 14.0 on end # SMBUS
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device pci 14.1 on end # IDE 0x439c
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device pci 14.2 on end # HDA 0x4383
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device pci 14.3 on # LPC 0x439d
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chip superio/smsc/lpc47n217
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device pnp 2e.3 off # Parallel
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.4 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.5 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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end #chip superio/smsc/lpc47n217
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end #device pci 14.3 # LPC
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device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO.
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device pci 14.5 on end # USB 2
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device pci 14.6 off end # Gec
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device pci 14.7 on end # SD
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device pci 15.0 off end # PCIe 0
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device pci 15.1 off end # PCIe 1
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device pci 15.2 off end # PCIe 2
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device pci 15.3 off end # PCIe 3
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end #chip southbridge/amd/agesa/hudson
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chip northbridge/amd/agesa/family15tn
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device pci 18.0 on end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.5 on end
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register "spdAddrLookup" = "
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{
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{ {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
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{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
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}"
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end
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end #domain
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end #chip northbridge/amd/agesa/family15tn/root_complex
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