Caveh Jalali d7468bfb27 xhci: Do not set the CRCR_CS bit ... We do not need to set the CS (Command Stop) bit in the Command Ring Control Register. CS is implied by CA (Command Abort). I'm not sure if there is a defined execution order for these command bits, so it's safer to only use the CA bit as it includes the CS function. Ref: xHCI spec 1.2 (May 2019), Section 5.4.5, Table 5-24. BUG=b:160354585,b:157123390 TEST=able to boot into recovery using USB stick on servo v2 on volteer as well as HooToo 8-1 hub Change-Id: Iaeba98b6da8da49f529358ca6d68270440ea0f42 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>		2020-08-31 06:38:53 +00:00
..
i8042	treewide: Remove "this file is part of" lines	2020-05-11 17:11:40 +00:00
serial	libpayload: Cache physical location of serial-console struct	2020-08-24 09:13:09 +00:00
storage	…
timer	…
udc	…
usb	xhci: Do not set the CRCR_CS bit	2020-08-31 06:38:53 +00:00
video	libpayload: cbgfx: Support buffered I/O	2020-08-28 21:40:58 +00:00
Makefile.inc	…
cbmem_console.c	libpayload: Cache physical cbmem console address	2020-08-24 09:12:47 +00:00
hid.c	…
mouse_cursor.c	…
nvram.c	…
options.c	libpayload: Cache physical CMOS option table location	2020-08-24 09:12:56 +00:00
pci.c	…
speaker.c	…