42b8835beb
So far POST codes were mapped on IO port 0x80 inside the NC FPGA which was connected via the LPC bus to the host CPU. On recent x86 generations the LPC bus was replaced with eSPI and not all Siemens boards have the eSPI routed to the NC FPGA. In order to have POST codes visible on those boards the display is accessible via PCI in addition. This patch adds the feature of sending the POST codes to the NC FPGA via a PCI mapped register. Change-Id: Ie15686de49cface17830365d78fe7c54cce183a0 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
12 lines
164 B
Text
12 lines
164 B
Text
config DRIVER_SIEMENS_NC_FPGA
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bool
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default n
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config NC_FPGA_NOTIFY_CB_READY
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bool
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default n
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config NC_FPGA_POST_CODE
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bool
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default n
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select EARLY_PCI_BRIDGE
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