coreboot-kgpe-d16/src/cpu/Kconfig
Subrata Banik 3c1b7b485b cpu: Enable per-CPUID microcode loading in CBFS
The current design of the `ucode-<variant>.bin` file combines all
possible microcode per cpuid into a unified blob. This model increases
the microcode loading time from RW CBFS due to higher CBFS verification
time (the bigger the CBFS binary the longer the verification takes).

This patch creates a provision to pack individual microcodes (per CPUID)
into the CBFS (RO and RWs). Implementation logic introduces
CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS config which relies on converting
Intel CPU microcode INC file into the binary file as per format
specified as in `cpu_microcode_$(CPUID).bin`.

For example: Intel CPU microcode `m506e3.inc` to convert into
`cpu_microcode_506e3.bin` binary file for coreboot to integrate if
CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS config is enabled.

Another config named CPU_INTEL_UCODE_SPLIT_BINARIES is used to specify
the directory name (including path) that holds the split microcode
binary files per CPUID for each coreboot variants.

For example: if google/kunimitsu had built with Intel SkyLake processor
with CPUID `506e3` and `506e4` then CPU_INTEL_UCODE_SPLIT_BINARIES
refers to the directory path that holds the split microcode binary
files aka cpu_microcode_506e3.bin and cpu_microcode_506e4.bin.

Refer to the file representation below:
|---3rdparty
|   |--- blobs
|   |    |--- mainboard
|   |    |   |--- google
|   |    |   |    |--- kunimitsu
|   |    |   |    |    |--- microcode_inputs
|   |    |   |    |    |    |--- kunimitsu
|   |    |   |    |    |    |    |--- cpu_microcode_506e3.bin
|   |    |   |    |    |    |    |--- cpu_microcode_506e4.bin

Users of this config option requires to manually place the microcode
binary files per CPUIDs as per the given format
(`cpu_microcode_$(CPUID).bin`) in a directory. Finally specify the
microcode binary directory path using CPU_UCODE_SPLIT_BINARIES config.

Additionally, modified the `find_cbfs_microcode()` logic to search
microcode from CBFS by CPUID. This change will improve the microcode
verification time from the CBFS, and will make it easier to update
individual microcodes.

BUG=b:242473942
TEST=emerge-rex sys-firmware/mtl-ucode-firmware-private
coreboot-private-files-baseboard-rex coreboot

Able to optimize ~10ms of boot time while loading microcode using
below configuration.

CONFIG_CPU_MICROCODE_CBFS_SPLIT_BINS=y
CONFIG_CPU_UCODE_SPLIT_BINARIES="3rdparty/blobs/mainboard/
               $(CONFIG_MAINBOARD_DIR)/microcode_inputs"

Without this patch:

  10:start of ramstage           1,005,139 (44)
  971:loading FSP-S              1,026,619 (21,479)

> RO/RW-A/RW-B CBFS contains unified cpu_microcode_blob.bin

  Name                           Offset     Type           Size   Comp
  ...
  cpu_microcode_blob.bin         0x1f740    microcode      273408 none
  intel_fit                      0x623c0    intel_fit          80 none
  ...
  ...
  bootblock                      0x3ee200   bootblock       32192 none

With this patch:

  10:start of ramstage           997,495 (43)
  971:loading FSP-S              1,010,148 (12,653)

> RO/RW-A/B CBFS that stores split microcode files per CPUID

  FMAP REGION: FW_MAIN_A
  Name                           Offset     Type           Size   Comp
  fallback/romstage              0x0        stage          127632 none
  cpu_microcode_a06a1.bin        0x1f340    microcode      137216 none
  cpu_microcode_a06a2.bin        0x40bc0    microcode      136192 none
  ...
  ...
  ecrw                           0x181280   raw            327680 none
  fallback/payload               0x1d1300   simple elf     127443 none

At reset, able to load the correct microcode using FIT table (RO CBFS)

  [NOTE ]  coreboot-coreboot-unknown.9999.3ad3153 Sat May 20 12:29:19
           UTC 2023 x86_32 bootblock starting (log level: 8)...
  [DEBUG]  CPU: Genuine Intel(R) 0000
  [DEBUG]  CPU: ID a06a1, MeteorLake A0, ucode: 00000016

Able to find `cpu_microcode_a06a1.bin` on google/rex with ES1 CPU
stepping (w/ CPUID 0xA06A1) (from RW CBFS)

  localhost ~ # cbmem -c -1 | grep microcode
  [DEBUG]  microcode: sig=0xa06a1 pf=0x80 revision=0x16
  [INFO ]  CBFS: Found 'cpu_microcode_a06a1.bin' @0x407c0 size 0x21800 in
           mcache @0x75c0d0e0
  [INFO ]  microcode: Update skipped, already up-to-date

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic7db73335ffa25399869cfb0d59129ee118f1012
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-08 12:06:00 +00:00

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# Warning: This file is included whether or not the if is here.
# The if controls how the evaluation occurs.
# (See also src/Kconfig)
source "src/cpu/*/Kconfig"
if ARCH_X86
config DCACHE_RAM_BASE
hex
config DCACHE_RAM_SIZE
hex
config DCACHE_BSP_STACK_SIZE
hex
config EARLYRAM_BSP_STACK_SIZE
depends on RESET_VECTOR_IN_RAM
hex
config SMP
bool
default y if MAX_CPUS != 1
default n
help
This option is used to enable certain functions to make coreboot
work correctly on symmetric multi processor (SMP) systems.
config SSE
bool
help
Select SSE in your socket or model Kconfig if your CPU has SSE
streaming SIMD instructions.
config SSE2
bool
default n
select SSE
help
Select SSE2 in your socket or model Kconfig if your CPU has SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.
endif # ARCH_X86
config SUPPORT_CPU_UCODE_IN_CBFS
bool
default n
config USES_MICROCODE_HEADER_FILES
def_bool n
select SUPPORT_CPU_UCODE_IN_CBFS
help
This is selected by a board or chipset to set the default for the
microcode source choice to a list of external microcode headers
config MICROCODE_BLOB_NOT_IN_BLOB_REPO
bool
help
Selected by platforms that don't maintain microcode updates in the
blobs repo yet.
config MICROCODE_BLOB_NOT_HOOKED_UP
bool
help
Selected by platforms that haven't hooked microcode updates up yet.
config MICROCODE_BLOB_UNDISCLOSED
bool
help
Selected by work-in-progress platforms that don't have microcode
updates available yet.
config USE_CPU_MICROCODE_CBFS_BINS
bool
help
Automatically selected below to add binary microcode files
(`cpu_microcode_bins` in the makefiles) to CBFS.
choice
prompt "Include CPU microcode in CBFS" if ARCH_X86
default CPU_MICROCODE_CBFS_EXTERNAL_HEADER if USES_MICROCODE_HEADER_FILES
default CPU_MICROCODE_CBFS_NONE if MICROCODE_BLOB_NOT_IN_BLOB_REPO || \
MICROCODE_BLOB_NOT_HOOKED_UP || \
MICROCODE_BLOB_UNDISCLOSED
depends on SUPPORT_CPU_UCODE_IN_CBFS && !CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS
config CPU_MICROCODE_CBFS_DEFAULT_BINS
bool "Generate from tree"
select USE_CPU_MICROCODE_CBFS_BINS
depends on !(MICROCODE_BLOB_NOT_IN_BLOB_REPO || \
MICROCODE_BLOB_NOT_HOOKED_UP || \
MICROCODE_BLOB_UNDISCLOSED)
help
Select this option if you want microcode updates to be assembled when
building coreboot and included in the final image as a separate CBFS
file. Microcode will not be hard-coded into ramstage.
The microcode file may be removed from the ROM image at a later
time with cbfstool, if desired.
If unsure, select this option.
config CPU_MICROCODE_CBFS_EXTERNAL_BINS
bool "Include external microcode binary"
select USE_CPU_MICROCODE_CBFS_BINS
help
Select this option if you want to include external binary files
in the CPUs native format. They will be included as a separate
file in CBFS.
A word of caution: only select this option if you are sure the
microcode that you have is newer than the microcode shipping with
coreboot.
The microcode file may be removed from the ROM image at a later
time with cbfstool, if desired.
If unsure, and applicable, select "Generate from tree"
config CPU_MICROCODE_CBFS_EXTERNAL_HEADER
bool "Include external microcode header files"
help
Select this option if you want to include external c header files
containing the CPU microcode. This will be included as a separate
file in CBFS.
A word of caution: only select this option if you are sure the
microcode that you have is newer than the microcode shipping with
coreboot.
The microcode file may be removed from the ROM image at a later
time with cbfstool, if desired.
If unsure, and applicable, select "Generate from tree"
config CPU_MICROCODE_CBFS_NONE
bool "Do not include microcode updates"
help
Select this option if you do not want CPU microcode included in CBFS.
Microcode may be added to the ROM image at a later time with cbfstool,
if desired.
If unsure, and applicable, select "Generate from tree"
The GOOD:
Microcode updates intend to solve issues that have been discovered
after CPU production. The expected effect is that systems work as
intended with the updated microcode, but we have also seen cases where
issues were solved by not applying microcode updates.
The BAD:
Note that some operating system include these same microcode patches,
so you may need to also disable microcode updates in your operating
system for this option to have an effect.
The UGLY:
A word of CAUTION: some CPUs depend on microcode updates to function
correctly. Not updating the microcode may leave the CPU operating at
less than optimal performance, or may cause outright hangups.
There are CPUs where coreboot cannot properly initialize the CPU
without microcode updates
For example, if running with the factory microcode, some Intel
SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
will hang when changing the frequency.
Make sure you have a way of flashing the ROM externally before
selecting this option.
endchoice
config CPU_MICROCODE_HEADER_FILES
string "List of space separated microcode header files with the path"
depends on CPU_MICROCODE_CBFS_EXTERNAL_HEADER
help
A list of one or more microcode header files with path from the
coreboot directory. These should be separated by spaces.
config CPU_UCODE_BINARIES
string "Microcode binary path and filename"
depends on CPU_MICROCODE_CBFS_EXTERNAL_BINS
default ""
help
Some platforms have microcode in the blobs directory, and these can
be hardcoded in the makefiles. For platforms with microcode
binaries that aren't in the makefile, set this option to pull
in the microcode.
This should contain the full path of the file for one or more
microcode binary files to include, separated by spaces.
If unsure, leave this blank.