8d2b49f1f7
The EHCI debug device setup code was removed from broadwell in
commit 49ee5ef: http://review.coreboot.org/11874
However the generic device setup code is in the southbridge/common/intel
directory while broadwell is in the soc directory so this is not used.
Add it back to the broadwell soc to fix undefined reference compile
errors with 'pci_ehci_dbg_dev' and 'pci_ehci_dbg_enable'.
This was tested to compile and produce romstage and ramstage output on a
google/samus board.
Change-Id: Ia93825a1e21a770f6c82d0989cb97980a5c700d6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12794
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
87 lines
2.6 KiB
Makefile
87 lines
2.6 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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ramstage-y += acpi.c
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ramstage-y += adsp.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += cpu_info.c
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smm-y += cpu_info.c
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ramstage-$(CONFIG_ELOG) += elog.c
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ramstage-y += finalize.c
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ramstage-y += gpio.c
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romstage-y += gpio.c
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smm-y += gpio.c
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ramstage-y += hda.c
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ramstage-y += igd.c
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ramstage-y += iobp.c
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romstage-y += iobp.c
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ramstage-y += lpc.c
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ramstage-y += me.c
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ramstage-y += me_status.c
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romstage-y += me_status.c
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ramstage-y += memmap.c
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romstage-y += memmap.c
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ramstage-y += minihd.c
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ramstage-y += monotonic_timer.c
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smm-y += monotonic_timer.c
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ramstage-y += pch.c
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romstage-y += pch.c
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ramstage-y += pcie.c
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ramstage-y += pei_data.c
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romstage-y += pei_data.c
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ramstage-y += pmutil.c
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romstage-y += pmutil.c
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smm-y += pmutil.c
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ramstage-y += ramstage.c
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ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
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ramstage-y += reset.c
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romstage-y += reset.c
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ramstage-y += sata.c
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ramstage-y += serialio.c
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ramstage-y += smbus.c
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ramstage-y += smbus_common.c
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romstage-y += smbus_common.c
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ramstage-y += smi.c
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smm-y += smihandler.c
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ramstage-y += smmrelocate.c
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ramstage-y += spi.c
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smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
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ramstage-y += stage_cache.c
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romstage-y += stage_cache.c
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ramstage-y += systemagent.c
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ramstage-y += tsc_freq.c
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romstage-y += tsc_freq.c
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smm-y += tsc_freq.c
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romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c
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ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
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ramstage-y += ehci.c
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ramstage-y += xhci.c
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smm-y += xhci.c
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ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
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cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
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CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
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# If an MRC file is an ELF file determine the entry address and first loadable
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# section offset in the file. Subtract the offset from the entry address to
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# determine the final location.
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mrcelfoffset = $(shell $(READELF_x86_32) -S -W $(CONFIG_MRC_FILE) | sed -e 's/\[ /[0/' | awk '$$3 ~ /PROGBITS/ { print "0x"$$5; exit }' )
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mrcelfentry = $(shell $(READELF_x86_32) -h -W $(CONFIG_MRC_FILE) | grep 'Entry point address' | awk '{print $$NF }')
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# Add memory reference code blob.
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cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin
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mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE))
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mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS))
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mrc.bin-type := mrc
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endif
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