Felix Held 3df6f41928 soc/amd/cezanne/include/southbridge: add some more PM register defines ... Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib109efe679560604ff8209b4177611eb2aa9ebdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/58068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2021-10-11 15:15:41 +00:00
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amd	soc/amd/cezanne/include/southbridge: add some more PM register defines	2021-10-11 15:15:41 +00:00
cavium	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
example	src: Introduce ARCH_ALL_STAGES_X86	2021-07-02 08:19:10 +00:00
intel	soc/intel/tigerlake: Add ACPI addition for USB4/TBT latency optimization	2021-10-11 12:46:39 +00:00
mediatek	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
nvidia	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
qualcomm	sc7280: Add SHRM firmware support	2021-10-07 09:03:05 +00:00
rockchip	mipi: Make panel init callback work directly on DSI transaction types	2021-09-11 01:42:47 +00:00
samsung	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
sifive	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
ti	soc/ti/am335x/mmc.c: Fix memset length argument	2021-04-04 09:58:26 +00:00
ucb