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coreboot-kgpe-d16/util/sconfig
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Raul E Rangel 3f3f53cd5e util/sconfig: Add LPC and ESPI buses 
Picasso has an LPC and eSPI bridge on the same PCI DEVFN. They can both
be active at the same time. This adds a way to specify which devices
belong on which bus.

i.e.,
device pci 14.3 on  # - D14F3 bridge
	device espi 0 on
		chip ec/google/chromeec
			device pnp 0c09.0 on end
		end
	end
	device lpc 0 on
	end
end

BUG=b:154445472
TEST=Built trembyle and saw static.c contained the espi bus.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 		2020-05-12 20:12:17 +00:00
..
Makefile.inc commonlib: Add commonlib/bsd 2020-01-28 06:36:13 +00:00
description.md util: Add description.md to each util 2018-07-26 13:26:50 +00:00
lex.yy.c_shipped util/sconfig: Add LPC and ESPI buses 2020-05-12 20:12:17 +00:00
main.c util/sconfig: Add LPC and ESPI buses 2020-05-12 20:12:17 +00:00
sconfig.h util/: Replace GPLv2 boiler plate with SPDX header 2020-05-09 21:22:08 +00:00
sconfig.l util/sconfig: Add LPC and ESPI buses 2020-05-12 20:12:17 +00:00
sconfig.tab.c_shipped util/sconfig: Add LPC and ESPI buses 2020-05-12 20:12:17 +00:00
sconfig.tab.h_shipped util/sconfig: Add LPC and ESPI buses 2020-05-12 20:12:17 +00:00
sconfig.y util/sconfig: Add LPC and ESPI buses 2020-05-12 20:12:17 +00:00