Marshall Dawson 3e4e4c5f88 soc/amd/stoneyridge: Fix DRAM clear check ... Explicitly add #include files to romstage.c to ensure sizes of the devicetree structures are correct. The AMD support headers have an open #pragma pack(1) which causes structure sizes to change based on include ordering in different compilation units. More concretely, this fixes a bug where dev->chip_info is incorrectly detected as 0. Also shorten a printk string to bring the source line within 80 columns. Change-Id: I1ed51cdbb8df387a453de6cb944b90538dac4431 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2017-11-13 17:21:56 +00:00
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common	soc/amd/stoneyridge: Use uint8_t as type for SPD address	2017-11-10 19:11:38 +00:00
stoneyridge	soc/amd/stoneyridge: Fix DRAM clear check	2017-11-13 17:21:56 +00:00
Kconfig	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00