d098575b0e
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
76 lines
2.3 KiB
C
76 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "sb800.h"
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static void pci_init(struct device *dev)
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{
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u32 dword;
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u8 byte;
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/* RPR 6.1 Enables the PCI-bridge subtractive decode */
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/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
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byte = pci_read_config8(dev, 0x4B);
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byte |= 1 << 7;
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pci_write_config8(dev, 0x4B, byte);
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byte = pci_read_config8(dev, 0x40);
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byte |= 1 << 5;
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pci_write_config8(dev, 0x40, byte);
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/* RPR6.2 PCI-bridge upstream dual address window */
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/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
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byte = pci_read_config8(dev, 0x50);
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byte |= 1 << 0;
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pci_write_config8(dev, 0x50, byte);
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/* RPR 6.3 Enable One-Prefetch-Channel Mode */
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dword = pci_read_config32(dev, 0x64);
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dword |= 1 << 20;
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pci_write_config32(dev, 0x64, dword);
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/* rpr6.4 Adjusting CLKRUN# */
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dword = pci_read_config32(dev, 0x64);
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dword |= (1 << 15);
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pci_write_config32(dev, 0x64, dword);
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = 0,
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};
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static struct device_operations pci_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.init = pci_init,
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.scan_bus = pci_scan_bridge,
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.reset_bus = pci_bus_reset,
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.ops_pci = &lops_pci,
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};
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static const struct pci_driver pci_driver __pci_driver = {
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.ops = &pci_ops,
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.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_SB800_PCI,
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};
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