b3ae1867d1
to unify calls to *_enable_usbdebug() * rename *_enable_usbdebug() to enable_usbdebug() * move enable_usbdebug() to generic romstage console init code and drop it from the individual romstage.c files. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
67 lines
2.1 KiB
C
67 lines
2.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SB800_H
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#define SB800_H
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#include <device/pci_ids.h>
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#include "chip.h"
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/* Power management index/data registers */
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#define BIOSRAM_INDEX 0xcd4
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#define BIOSRAM_DATA 0xcd5
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#define PM_INDEX 0xcd6
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#define PM_DATA 0xcd7
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#define PM2_INDEX 0xcd0
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#define PM2_DATA 0xcd1
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#define SB800_ACPI_IO_BASE 0x800
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#define ACPI_PM_EVT_BLK (SB800_ACPI_IO_BASE + 0x00) /* 4 bytes */
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#define ACPI_PM1_CNT_BLK (SB800_ACPI_IO_BASE + 0x04) /* 2 bytes */
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#define ACPI_PMA_CNT_BLK (SB800_ACPI_IO_BASE + 0x0F) /* 1 byte */
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#define ACPI_PM_TMR_BLK (SB800_ACPI_IO_BASE + 0x18) /* 4 bytes */
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#define ACPI_GPE0_BLK (SB800_ACPI_IO_BASE + 0x10) /* 8 bytes */
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#define ACPI_CPU_CONTROL (SB800_ACPI_IO_BASE + 0x08) /* 6 bytes */
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void pm_iowrite(u8 reg, u8 value);
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u8 pm_ioread(u8 reg);
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void pm2_iowrite(u8 reg, u8 value);
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u8 pm2_ioread(u8 reg);
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void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
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#define REV_SB800_A11 0x11
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#define REV_SB800_A12 0x12
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#ifdef __PRE_RAM__
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void sb800_lpc_port80(void);
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void sb800_pci_port80(void);
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void sb800_clk_output_48Mhz(void);
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int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
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int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
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void enable_usbdebug(unsigned int port);
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#else
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void sb800_enable(device_t dev);
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void __attribute__((weak)) sb800_setup_sata_phys(struct device *dev);
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#endif
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#endif /* SB800_H */
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