3ee7453e0e
The C state ACPI packages binaryPI generates and passes to coreboot in the PSTATE SSDT only include the C2 state, but the kernel will add the C1 state to its usable C states in this case. The native C state code will generate both the C1 and C2 state packages to be more complete and also to be more in line with the other AMD SoCs. The code added in this commit isn't used yet, but will be used as soon as Stoneyridge will be using the common AMD generate_cpu_entries by selecting SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE once all needed helper functions are implemented for Stoneyridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I06f90306ac196704e0102d0da6eab03f51513c29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> |
||
|---|---|---|
| .. | ||
| amd | ||
| cavium | ||
| example/min86 | ||
| intel | ||
| mediatek | ||
| nvidia | ||
| qualcomm | ||
| rockchip | ||
| samsung | ||
| sifive/fu540 | ||
| ti | ||
| ucb/riscv | ||