No description
3f57548625
from 2.6.30 (?)
the new vmlinux with per_cpu and brk support will have more sections.
Elf file type is EXEC (Executable file)
Entry point 0x200000
There are 7 program headers, starting at offset 64
Program Headers:
Type Offset VirtAddr PhysAddr
FileSiz MemSiz Flags Align
LOAD 0x0000000000200000 0xffffffff80200000 0x0000000000200000
0x0000000000e46000 0x0000000000e46000 R E 200000
LOAD 0x0000000001046000 0xffffffff81046000 0x0000000001046000
0x00000000001406e0 0x00000000001406e0 RWE 200000
LOAD 0x0000000001200000 0xffffffffff600000 0x0000000001187000
0x0000000000000888 0x0000000000000888 RWE 200000
LOAD 0x0000000001388000 0xffffffff81188000 0x0000000001188000
0x000000000008a086 0x000000000008a086 RWE 200000
LOAD 0x0000000001600000 0x0000000000000000 0x0000000001213000
0x0000000000015e20 0x0000000000015e20 RWE 200000
LOAD 0x0000000001629000 0xffffffff81229000 0x0000000001229000
0x0000000000000000 0x0000000000208000 RWE 200000
NOTE 0x0000000000b3c7e8 0xffffffff80b3c7e8 0x0000000000b3c7e8
0x0000000000000024 0x0000000000000024 4
Section to Segment mapping:
Segment Sections...
00 .text .notes __ex_table .rodata __bug_table .pci_fixup .builtin_fw __ksymtab __ksymtab_gpl __ksymtab_strings __init_rodata __param
01 .data .init.rodata .data.cacheline_aligned .data.read_mostly
02 .vsyscall_0 .vsyscall_fn .vsyscall_gtod_data .vsyscall_1 .vsyscall_2 .vgetcpu_mode .jiffies
03 .data.init_task .smp_locks .init.text .init.data .init.setup .initcall.init .con_initcall.init .x86_cpu_dev.init .altinstructions .altinstr_replacement .exit.text .init.ramfs
04 .data.percpu
05 .bss .brk
06 .notes
So need to increase NR_SECTIONS.
also fix one typo about phys address mask.
Peter says: A similar fix was also implemented by Maciej Pijanka, so let's
commit this now, eh.
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4377 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
||
|---|---|---|
| documentation | ||
| payloads | ||
| src | ||
| targets | ||
| util | ||
| COPYING | ||
| NEWS | ||
| README | ||
------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS you can find in most of today's computers. It performs just a little bit of hardware initialization and then executes one of many possible payloads, e.g. a Linux kernel or a bootloader. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * gcc / g++ * make * python * perl Optional: * doxygen (for generating/viewing documentation) * iasl (for targets with ACPI support) * gdb (for better debugging facilities on some targets) Building coreboot ----------------- Please consult http://www.coreboot.org/Documentation for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------- If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files (mostly those derived from the Linux kernel) are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.