481c52ddd5
Bootguard sets up CAR/NEM on its own so the only thing needed is to find free MTRRs for our own CAR region and clear that area to fill in cache lines. TESTED on prodrive/hermes with bootguard enabled. Change-Id: Ifac5267f8f4b820a61519fb4a497e2ce7075cc40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
36 lines
957 B
C
36 lines
957 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef CPU_INTEL_MSR_H
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#define CPU_INTEL_MSR_H
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/*
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* Common MSRs for Intel CPUs
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*/
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#define MSR_PIC_MSG_CONTROL 0x2e
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#define TPR_UPDATES_DISABLE (1 << 10)
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#define MSR_PLATFORM_INFO 0xce
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#define MSR_BC_PBEC 0x139
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#define B_STOP_PBET (1 << 0)
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#define MSR_BOOT_GUARD_SACM_INFO 0x13a
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#define V_TPM_PRESENT_MASK 0x06
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#define B_BOOT_GUARD_SACM_INFO_NEM_ENABLED (1 << 0)
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#define B_BOOT_GUARD_SACM_INFO_TPM_SUCCESS (1 << 3)
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#define B_BOOT_GUARD_SACM_INFO_MEASURED_BOOT (1 << 5)
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#define B_BOOT_GUARD_SACM_INFO_VERIFIED_BOOT (1 << 6)
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#define B_BOOT_GUARD_SACM_INFO_REVOKED (1 << 7)
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#define B_BOOT_GUARD_SACM_INFO_BTG_CAPABILITY (1ull << 32)
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#define B_BOOT_GUARD_SACM_INFO_TXT_CAPABILITY (1ull << 34)
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#define MSR_FEATURE_CONFIG 0x13c
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#define AESNI_DISABLE (1 << 1)
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#define AESNI_LOCK (1 << 0)
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#define MSR_SPCL_CHIPSET_USAGE 0x1fe
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#define MSR_PKG_C10_RESIDENCY 0x632
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#endif /* CPU_INTEL_MSR_H */
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