b4d3d09ded
Asserting this GPIO will send a signal to the EC to trigger a reset
for the AP and the CR50.
BRANCH=none
BUG=chrome-os-partner:55252
TEST=the device now reboots when it needs to switch between different
boot modes instead of hanging with "failed to reboot" message.
Change-Id: I8d168e313b6983c96c80f7ad6d70bb84c1ec1d9c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 83a4c8ff68ab24a103f2166e948eb23624ea97f7
Original-Change-Id: Idfd20977cf3682bd8933f89e8eec53005e55864e
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/360238
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15718
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
34 lines
986 B
Makefile
34 lines
986 B
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright 2016 Rockchip Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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bootblock-y += bootblock.c
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bootblock-y += chromeos.c
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bootblock-y += memlayout.ld
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verstage-y += chromeos.c
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verstage-y += memlayout.ld
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verstage-y += reset.c
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romstage-y += boardid.c
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romstage-y += chromeos.c
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romstage-y += memlayout.ld
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romstage-y += sdram_configs.c
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ramstage-y += boardid.c
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ramstage-y += chromeos.c
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ramstage-y += mainboard.c
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ramstage-y += memlayout.ld
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ramstage-y += reset.c
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ramstage-y += sdram_configs.c # Needed for ram_code()
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