14e2277962
while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
130 lines
2.9 KiB
C
130 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <console/console.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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/* ********************* smi_util ************************* */
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/* Data */
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#define UART_RBR 0x00
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#define UART_TBR 0x00
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/* Control */
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#define UART_IER 0x01
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#define UART_IIR 0x02
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#define UART_FCR 0x02
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#define UART_LCR 0x03
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#define UART_MCR 0x04
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#define UART_DLL 0x00
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#define UART_DLM 0x01
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/* Status */
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#define UART_LSR 0x05
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#define UART_MSR 0x06
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#define UART_SCR 0x07
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#ifndef CONFIG_TTYS0_BASE
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#define CONFIG_TTYS0_BASE 0x3f8
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#endif
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#ifndef CONFIG_TTYS0_BAUD
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#define CONFIG_TTYS0_BAUD 115200
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#endif
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#ifndef CONFIG_TTYS0_DIV
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#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
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#endif
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/* Line Control Settings */
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#ifndef CONFIG_TTYS0_LCS
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/* Set 8bit, 1 stop bit, no parity */
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#define CONFIG_TTYS0_LCS 0x3
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#endif
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#define UART_LCS CONFIG_TTYS0_LCS
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static int uart_can_tx_byte(void)
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{
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return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
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}
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static void uart_wait_to_tx_byte(void)
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{
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while(!uart_can_tx_byte())
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;
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}
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static void uart_wait_until_sent(void)
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{
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while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
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;
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}
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static void uart_tx_byte(unsigned char data)
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{
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uart_wait_to_tx_byte();
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outb(data, CONFIG_TTYS0_BASE + UART_TBR);
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/* Make certain the data clears the fifos */
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uart_wait_until_sent();
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}
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void console_tx_flush(void)
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{
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uart_wait_to_tx_byte();
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}
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void console_tx_byte(unsigned char byte)
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{
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if (byte == '\n')
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uart_tx_byte('\r');
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uart_tx_byte(byte);
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}
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#if CONFIG_DEBUG_SMI
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static void uart_init(void)
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{
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/* disable interrupts */
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outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
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/* enable fifo's */
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outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
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/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
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outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
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outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
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outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
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outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
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}
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#endif
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void console_init(void)
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{
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#if CONFIG_DEBUG_SMI
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console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
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uart_init();
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#else
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console_loglevel = 1;
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#endif
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}
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/* ********************* smi_util ************************* */
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