40f36e0d8d
The Agesa wrapper and UDELAY_TIMER2 define their own timer functions, so don't shove in UDELAY_IO Change-Id: Ibe3345e825e0c074d5f531dba1198cd6e7b0a42d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1864 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
65 lines
970 B
Text
65 lines
970 B
Text
config SERIAL_CPU_INIT
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bool
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default y
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config UDELAY_IO
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bool
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default y if !UDELAY_LAPIC && !UDELAY_TSC && !UDELAY_TIMER2
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default n
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config UDELAY_LAPIC
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bool
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default n
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config UDELAY_TSC
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bool
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default n
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config UDELAY_TIMER2
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bool
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default n
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config TSC_CALIBRATE_WITH_IO
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bool
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default n
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config TSC_SYNC_LFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an lfence instruction in order to synchronize
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rdtsc. This is true for all modern AMD CPUs.
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config TSC_SYNC_MFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an mfence instruction in order to synchronize
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rdtsc. This is true for all modern Intel CPUs.
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config XIP_ROM_SIZE
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hex
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default ROM_SIZE if ROMCC
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default 0x10000
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config CPU_ADDR_BITS
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int
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default 36
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config LOGICAL_CPUS
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bool
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default y
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config CACHE_ROM
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bool
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default n
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config SMM_TSEG
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bool
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default n
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config SMM_TSEG_SIZE
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hex
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default 0
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