a46a712610
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
295 lines
8.5 KiB
Text
295 lines
8.5 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
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* Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* ISA portions taken from QEMU acpi-dsdt.dsl.
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*/
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DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
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{
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#include "northbridge/amd/amdk8/util.asl"
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/* For now only define 2 power states:
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* - S0 which is fully on
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* - S5 which is soft off
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* Any others would involve declaring the wake up methods.
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*/
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Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
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Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
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/* Root of the bus hierarchy */
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Scope (\_SB)
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{
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/* Top PCI device (CK804) */
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Device (PCI0)
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{
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Name (_HID, EisaId ("PNP0A03"))
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Name (_ADR, 0x00)
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Name (_UID, 0x00)
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Name (_BBN, 0x00)
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External (BUSN)
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External (MMIO)
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External (PCIO)
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External (SBLK)
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External (TOM1)
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External (HCLK)
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External (SBDN)
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External (HCDN)
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF0, ResourceTemplate ()
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{
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IO (Decode16,
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0x0CF8, // Address Range Minimum
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0x0CF8, // Address Range Maximum
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0x01, // Address Alignment
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0x08, // Address Length
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)
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Address Space Granularity
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0x0000, // Address Range Minimum
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0x0CF7, // Address Range Maximum
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0x0000, // Address Translation Offset
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0x0CF8, // Address Length
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,, , TypeStatic)
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})
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/* Methods bellow use SSDT to get actual MMIO regs
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The IO ports are from 0xd00, optionally an VGA,
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otherwise the info from MMIO is used.
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\_SB.GXXX(node, link)
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*/
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Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
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Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
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Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
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Return (Local3)
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}
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/* PCI Routing Table */
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Name (_PRT, Package () {
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/* Since source is 0, index is IRQ. */
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/* in ABCD, A=0, B=1, C=2, D=3 */
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/* SlotFFFF, ABCD, source, index */
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Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */
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Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */
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Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */
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Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */
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Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */
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})
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Device (PCIL)
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{
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Name (_ADR, 0x00090000)
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Name (_UID, 0x00)
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Name (_BBN, 0x01)
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Name (_PRT, Package () {
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Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, /* 1:04 PCI 32 IRQ16-IRQ19 */
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Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
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Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
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Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
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Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 }, /* 1:06 Onboard ATI Rage IRQ 18 */
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Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x12 }, /* 1:08 Onboard Intel NIC IRQ 18 */
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})
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}
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/* 2:00 PCIe x16 SB IRQ 18 */
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Device (PE16)
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{
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Name (_ADR, 0x000e0000)
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Name (_UID, 0x00)
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Name (_BBN, 0x02)
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Name (_PRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
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})
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}
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/* 2:00 PCIe x4 SB IRQ 17 */
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Device (PE4)
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{
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Name (_ADR, 0x000e0000)
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Name (_UID, 0x00)
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Name (_BBN, 0x02)
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Name (_PRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* PCIE IRQ16-IRQ19 */
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
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})
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}
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Device (ISA) {
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Name (_HID, EisaId ("PNP0A05"))
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Name (_ADR, 0x00010000)
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/* PS/2 keyboard (seems to be important for WinXP install) */
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Device (KBD)
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{
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Name (_HID, EisaId ("PNP0303"))
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0f)
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (TMP, ResourceTemplate () {
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IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
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IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
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IRQNoFlags () {1}
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})
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Return (TMP)
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}
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}
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/* PS/2 mouse */
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Device (MOU)
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{
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Name (_HID, EisaId ("PNP0F13"))
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0f)
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (TMP, ResourceTemplate () {
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IRQNoFlags () {12}
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})
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Return (TMP)
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}
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}
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/* Parallel port */
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Device (LP0)
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{
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Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0f)
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (TMP, ResourceTemplate () {
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FixedIO (0x0378, 0x10)
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IRQNoFlags () {7}
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})
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Return (TMP)
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}
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}
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/* Floppy controller */
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Device (FDC0)
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{
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Name (_HID, EisaId ("PNP0700"))
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0f)
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF0, ResourceTemplate () {
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FixedIO (0x03F0, 0x08)
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IRQNoFlags () {6}
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DMA (Compatibility, NotBusMaster, Transfer8) {2}
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})
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Return (BUF0)
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}
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}
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}
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}
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/* AMD 8131 PCI-X tunnel */
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Device (PCI2)
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{
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Name (_HID, EisaId ("PNP0A03"))
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Name (_ADR, 0x00)
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Name (_UID, 0x00)
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Name (_BBN, 0x40)
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/* There is no _PRT Here because I don't know what to
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* put in it. Since the 8131 has its own APIC, it
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* isn't wired to other IRQs. */
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF0, ResourceTemplate ()
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{
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IO (Decode16,
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0x0CF8, // Address Range Minimum
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0x0CF8, // Address Range Maximum
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0x01, // Address Alignment
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0x08, // Address Length
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)
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})
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/* Methods bellow use SSDT to get actual MMIO regs
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The IO ports are from 0xd00, optionally an VGA,
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otherwise the info from MMIO is used.
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\_SB.GXXX(node, link)
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*/
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Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1)
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Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2)
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Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3)
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Return (Local3)
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}
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/* Channel A PCIX 133 */
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Device (PCXF)
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{
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Name (_ADR, 0x00000000)
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Name (_UID, 0x00)
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Name (_BBN, 0x41)
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Name (_PRT, Package () {
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Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1b }, /* PCIE IRQ24-IRQ27 shifted 3*/
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Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 },
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Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 },
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Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1a },
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Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1a }, /* PCIE IRQ24-IRQ27 shifted 2*/
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Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1b },
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Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 },
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Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 },
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})
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}
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/* Channel B PCIX 100 */
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Device (PCXS) /* Onboard NIC, SO-DIMM, Slot 4 */
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{
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Name (_ADR, 0x00010000)
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Name (_UID, 0x00)
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Name (_BBN, 0x42)
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Name (_PRT, Package () {
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Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */
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Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1d },
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Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1e },
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Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1f },
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Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */
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Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x1d },
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Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x1e },
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Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x1f },
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Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1d }, /* PCIE IRQ28-IRQ31 shifted 2 */
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Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1e },
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Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1f },
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Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1c },
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})
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}
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}
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}
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}
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