99b024db88
The xHCI controller's MMIO space has a length of 64KiB not 4KiB. Therefore, setting the xHCI BAR to 0xe8001000 worked the same like setting it to 0xe8000000, as bit12 is reserved and ignored. This again interfered with the MMIO space of the first EHCI controller and broke S3 resume on Ivy Bridge. AFAIK, the MRC ignores the setting of the xHCI BAR, anyway. So just drop these lines. Change-Id: I8af9c2ba34133f15636a9056fc8880b3b6ab95e0 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3521 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
56 lines
1.7 KiB
C
56 lines
1.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/pci_ids.h>
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#include <device/pci_def.h>
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#include "pch.h"
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#define PCH_EHCI1_TEMP_BAR0 0xe8000000
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#define PCH_EHCI2_TEMP_BAR0 0xe8000400
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/*
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* Setup USB controller MMIO BAR to prevent the
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* reference code from resetting the controller.
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*
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* The BAR will be re-assigned during device
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* enumeration so these are only temporary.
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*/
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void enable_usb_bar(void)
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{
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device_t usb0 = PCH_EHCI1_DEV;
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device_t usb1 = PCH_EHCI2_DEV;
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u32 cmd;
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/* USB Controller 1 */
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pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
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PCH_EHCI1_TEMP_BAR0);
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cmd = pci_read_config32(usb0, PCI_COMMAND);
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config32(usb0, PCI_COMMAND, cmd);
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/* USB Controller 2 */
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pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
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PCH_EHCI2_TEMP_BAR0);
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cmd = pci_read_config32(usb1, PCI_COMMAND);
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config32(usb1, PCI_COMMAND, cmd);
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}
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