bc140cf111
The code in mrc_cache.c doesn't check for the presence of 'mrc.cache', and just returns hardcoded value for he location of he MRC cache. This becomes a problem when there is a CBFS file at the same location, which can get overwritten. A CBFS file is created to cover this region so that nothing can be added there. This has the advantage of creating a build time error if another cbfs file is hardcoded over the same region. The default location of the MRC cache is also moved to 4G - 128K to ensure that it defaults to something within CBFS. Change-Id: Ic029c182f5a2180cb680e09b25165ee303a448a3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11440 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
72 lines
1.4 KiB
Text
72 lines
1.4 KiB
Text
config SOC_INTEL_COMMON
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bool
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help
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common code for Intel SOCs
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if SOC_INTEL_COMMON
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config CACHE_MRC_SETTINGS
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bool "Save cached MRC settings"
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default n
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help
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If CONFIG_USE_FMAP is enabled, it is assumed that a flashmap
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containing an RW_MRC_CACHE entry that specifies the location and size
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of the cache will be added to the image and present at runtime.
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if CACHE_MRC_SETTINGS
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config MRC_SETTINGS_CACHE_BASE
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hex
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depends on !USE_FMAP
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default 0xfffe0000
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config MRC_SETTINGS_CACHE_SIZE
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hex
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depends on !USE_FMAP
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default 0x10000
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config MRC_SETTINGS_PROTECT
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bool "Enable protection on MRC settings"
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depends on !USE_FMAP
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default n
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endif # CACHE_MRC_SETTINGS
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config DISPLAY_MTRRS
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bool "MTRRs: Display the MTRR settings"
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default n
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config DISPLAY_SMM_MEMORY_MAP
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bool "SMM: Display the SMM memory map"
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default n
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config SOC_INTEL_COMMON_FSP_RAM_INIT
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bool "FSP: Use the common raminit.c module"
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default n
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depends on PLATFORM_USES_FSP1_1
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config SOC_INTEL_COMMON_FSP_ROMSTAGE
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bool
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default n
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depends on PLATFORM_USES_FSP1_1
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config SOC_INTEL_COMMON_RESET
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bool
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default n
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config SOC_INTEL_COMMON_STACK
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bool
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default n
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depends on PLATFORM_USES_FSP1_1
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config SOC_INTEL_COMMON_STAGE_CACHE
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bool
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default n
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depends on PLATFORM_USES_FSP1_1
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config ROMSTAGE_RAM_STACK_SIZE
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hex "Size of the romstage RAM stack in bytes"
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default 0x5000
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depends on SOC_INTEL_COMMON_STACK
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endif # SOC_INTEL_COMMON
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