coreboot-kgpe-d16/src/soc/intel
Duncan Laurie 4234ca2764 soc/intel/skylake: Include I2C code in romstage
The lpss_i2c driver is enabled in romstage, so the SOC needs to
export the pre-ram compatible I2C controller info, which for
skylake is in the bootblock/i2c.c file.

This was not causing a compiler error in normal use, but when
adding I2C debug code in romstage it failed to compile.
With this added, I can now do I2C transactions in romstage.

Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18198
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22 19:24:37 +01:00
..
apollolake soc/intel/apollolake: correct GPIO 13 IRQ number 2017-01-21 21:45:17 +01:00
baytrail
braswell intel: Fix copy/paste error in license text 2017-01-16 12:57:05 +01:00
broadwell cpu/intel/common: Add/Use common function to set virtualization 2016-12-27 02:30:08 +01:00
common
fsp_baytrail fsp_baytrail: Enable graphic init per default 2017-01-13 17:42:26 +01:00
fsp_broadwell_de intel: Fix copy/paste error in license text 2017-01-16 12:57:05 +01:00
quark intel: Fix copy/paste error in license text 2017-01-16 12:57:05 +01:00
sch nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h> 2017-01-06 18:15:03 +01:00
skylake soc/intel/skylake: Include I2C code in romstage 2017-01-22 19:24:37 +01:00