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430bf0d8a9
This adds the option to put LPSS and SCC devices into ACPI mode by saving their BAR0 and BAR1 base addresses in a new device NVS structure that is placed at offset 0x1000 within the global NVS table. The Chrome NVS strcture is padded out to 0xf00 bytes so there is a clean offset to work with as it will need to be used by depthcharge to know what addresses devices live at. A few ACPI Mode IRQs are fixed up, DMA1 and DMA2 are swapped and the EMMC 4.5 IRQ is changed to 44. New ACPI code is provided to instantiate the LPSS and SCC devices with the magic HID values from Intel so the kernel drivers can locate and use them. The default is still for devices to be in PCI mode so this does not have any real effect without it being enabled in the mainboard devicetree. Note: this needs the updated IASL compiler which is in the CQ now because it uses the FixedDMA() ACPI operator. BUG=chrome-os-partner:23505,chrome-os-partner:24380 CQ-DEPEND=CL:179459,CL:179364 BRANCH=none TEST=manual tests on rambi device: 1) build and boot with devices still in PCI mode and ensure that nothing is changed 2) enable lpss_acpi_mode and see I2C devices detected by the kernel in ACPI mode. Note that by itself this breaks trackpad probing so that will need to be implemented before it is enabled. 3) enable scc_acpi_mode and see EMMC and SDCard devices detected by the kernel in ACPI mode. Note that this breaks depthcharge use of the EMMC because it is not longer discoverable as a PCI device. Change-Id: I2a007f3c4e0b06ace5172a15c696a8eaad41ed73 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179481 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5004 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> |
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| 3rdparty@324ec3cb64 | ||
| documentation | ||
| payloads | ||
| src | ||
| util | ||
| .gitignore | ||
| .gitmodules | ||
| .gitreview | ||
| COPYING | ||
| Makefile | ||
| Makefile.inc | ||
| README | ||
| toolchain.inc | ||
------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * gcc / g++ * make Optional: * doxygen (for generating/viewing documentation) * iasl (for targets with ACPI support) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.