coreboot-kgpe-d16/src/soc/amd/picasso/tsc_freq.c
Marshall Dawson 80d0b01b38 soc/amd/picasso: Update TSC and monotonic timer
Picasso's TimeStamp Counter is a new design and different than
Stoney Ridge.  Although advertised as invariant, the ST TSC did
not become so until midway through POST making it an unreliable
source for measuring time.  This is not the case for Picasso.

Remove the Stoney Ridge monotonic timer code and rely on the TSC.

Modify the calculation used in Family 15h of finding the number
of boost states first, and get the frequency directly out of the
Pstate0 register.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I909743483309279eb8c3bf68852d6082381f0dff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-09-09 22:20:08 +00:00

45 lines
1.2 KiB
C

/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Intel Corp.
* Copyright (C) 2017 Advanced Micro Devices
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/tsc.h>
#include <console/console.h>
static unsigned long mhz;
unsigned long tsc_freq_mhz(void)
{
msr_t msr;
uint8_t cpufid;
uint8_t cpudid;
uint8_t high_state;
if (mhz)
return mhz;
high_state = rdmsr(PS_LIM_REG).lo & 0x7;
msr = rdmsr(PSTATE_0_MSR + high_state);
if (!(msr.hi & 0x80000000))
die("Unknown error: cannot determine P-state 0\n");
cpufid = (msr.lo & 0x3f);
cpudid = (msr.lo & 0x1c0) >> 6;
mhz = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
return mhz;
}