1259 lines
36 KiB
C
1259 lines
36 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* It was originally based on the Linux kernel (drivers/pci/pci.c).
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*
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* Modifications are:
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* Copyright (C) 2003-2004 Linux Networx
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* (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
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* Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
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* Copyright (C) 2005-2006 Tyan
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* (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
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* Copyright (C) 2005-2009 coresystems GmbH
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* (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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*/
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/*
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* PCI Bus Services, see include/linux/pci.h for further explanation.
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*
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* Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
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* David Mosberger-Tang
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*
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* Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
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*/
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#include <console/console.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <bitops.h>
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#include <string.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <part/hard_reset.h>
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#include <part/fallback_boot.h>
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#include <delay.h>
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#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
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#include <device/hypertransport.h>
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#endif
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#if CONFIG_PCIX_PLUGIN_SUPPORT == 1
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#include <device/pcix.h>
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#endif
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#if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
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#include <device/pciexp.h>
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#endif
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#if CONFIG_AGP_PLUGIN_SUPPORT == 1
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#include <device/agp.h>
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#endif
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#if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
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#include <device/cardbus.h>
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#endif
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#define CONFIG_PC80_SYSTEM 1
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#if CONFIG_PC80_SYSTEM == 1
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#include <pc80/i8259.h>
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#endif
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u8 pci_moving_config8(struct device *dev, unsigned int reg)
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{
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u8 value, ones, zeroes;
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value = pci_read_config8(dev, reg);
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pci_write_config8(dev, reg, 0xff);
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ones = pci_read_config8(dev, reg);
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pci_write_config8(dev, reg, 0x00);
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zeroes = pci_read_config8(dev, reg);
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pci_write_config8(dev, reg, value);
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return ones ^ zeroes;
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}
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u16 pci_moving_config16(struct device * dev, unsigned int reg)
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{
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u16 value, ones, zeroes;
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value = pci_read_config16(dev, reg);
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pci_write_config16(dev, reg, 0xffff);
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ones = pci_read_config16(dev, reg);
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pci_write_config16(dev, reg, 0x0000);
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zeroes = pci_read_config16(dev, reg);
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pci_write_config16(dev, reg, value);
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return ones ^ zeroes;
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}
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u32 pci_moving_config32(struct device * dev, unsigned int reg)
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{
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u32 value, ones, zeroes;
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value = pci_read_config32(dev, reg);
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pci_write_config32(dev, reg, 0xffffffff);
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ones = pci_read_config32(dev, reg);
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pci_write_config32(dev, reg, 0x00000000);
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zeroes = pci_read_config32(dev, reg);
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pci_write_config32(dev, reg, value);
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return ones ^ zeroes;
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}
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/**
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* Given a device, a capability type, and a last position, return the next
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* matching capability. Always start at the head of the list.
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*
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* @param dev Pointer to the device structure.
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* @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for.
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* @param last Location of the PCI capability register to start from.
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*/
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unsigned pci_find_next_capability(struct device *dev, unsigned cap,
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unsigned last)
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{
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unsigned pos = 0;
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unsigned status;
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unsigned reps = 48;
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status = pci_read_config16(dev, PCI_STATUS);
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if (!(status & PCI_STATUS_CAP_LIST)) {
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return 0;
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}
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switch (dev->hdr_type & 0x7f) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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pos = PCI_CAPABILITY_LIST;
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break;
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case PCI_HEADER_TYPE_CARDBUS:
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pos = PCI_CB_CAPABILITY_LIST;
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break;
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default:
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return 0;
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}
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pos = pci_read_config8(dev, pos);
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while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */
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int this_cap;
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pos &= ~3;
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this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
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printk_spew("Capability: type 0x%02x @ 0x%02x\n", this_cap,
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pos);
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if (this_cap == 0xff) {
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break;
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}
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if (!last && (this_cap == cap)) {
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return pos;
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}
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if (last == pos) {
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last = 0;
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}
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pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
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}
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return 0;
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}
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/**
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* Given a device, and a capability type, return the next matching
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* capability. Always start at the head of the list.
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*
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* @param dev Pointer to the device structure.
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* @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for.
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*/
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unsigned pci_find_capability(device_t dev, unsigned cap)
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{
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return pci_find_next_capability(dev, cap, 0);
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}
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/**
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* Given a device and register, read the size of the BAR for that register.
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*
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* @param dev Pointer to the device structure.
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* @param index Address of the PCI configuration register.
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*/
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struct resource *pci_get_resource(struct device *dev, unsigned long index)
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{
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struct resource *resource;
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unsigned long value, attr;
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resource_t moving, limit;
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/* Initialize the resources to nothing. */
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resource = new_resource(dev, index);
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/* Get the initial value. */
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value = pci_read_config32(dev, index);
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/* See which bits move. */
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moving = pci_moving_config32(dev, index);
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/* Initialize attr to the bits that do not move. */
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attr = value & ~moving;
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/* If it is a 64bit resource look at the high half as well. */
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if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
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((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
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PCI_BASE_ADDRESS_MEM_LIMIT_64)) {
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/* Find the high bits that move. */
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moving |=
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((resource_t) pci_moving_config32(dev, index + 4)) << 32;
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}
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/* Find the resource constraints.
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* Start by finding the bits that move. From there:
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* - Size is the least significant bit of the bits that move.
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* - Limit is all of the bits that move plus all of the lower bits.
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* See PCI Spec 6.2.5.1.
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*/
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limit = 0;
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if (moving) {
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resource->size = 1;
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resource->align = resource->gran = 0;
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while (!(moving & resource->size)) {
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resource->size <<= 1;
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resource->align += 1;
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resource->gran += 1;
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}
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resource->limit = limit = moving | (resource->size - 1);
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}
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/* Some broken hardware has read-only registers that do not
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* really size correctly.
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* Example: the Acer M7229 has BARs 1-4 normally read-only.
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* so BAR1 at offset 0x10 reads 0x1f1. If you size that register
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* by writing 0xffffffff to it, it will read back as 0x1f1 -- a
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* violation of the spec.
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* We catch this case and ignore it by observing which bits move,
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* This also catches the common case unimplemented registers
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* that always read back as 0.
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*/
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if (moving == 0) {
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if (value != 0) {
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printk_debug
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("%s register %02lx(%08lx), read-only ignoring it\n",
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dev_path(dev), index, value);
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}
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resource->flags = 0;
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} else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
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/* An I/O mapped base address. */
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attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
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resource->flags |= IORESOURCE_IO;
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/* I don't want to deal with 32bit I/O resources. */
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resource->limit = 0xffff;
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} else {
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/* A Memory mapped base address. */
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attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
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resource->flags |= IORESOURCE_MEM;
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if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
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resource->flags |= IORESOURCE_PREFETCH;
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}
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attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
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if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
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/* 32bit limit. */
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resource->limit = 0xffffffffUL;
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} else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
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/* 1MB limit. */
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resource->limit = 0x000fffffUL;
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} else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
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/* 64bit limit. */
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resource->limit = 0xffffffffffffffffULL;
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resource->flags |= IORESOURCE_PCI64;
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} else {
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/* Invalid value. */
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printk_err("Broken BAR with value %lx\n", attr);
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printk_err(" on dev %s at index %02lx\n",
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dev_path(dev), index);
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resource->flags = 0;
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}
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}
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/* Don't let the limit exceed which bits can move. */
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if (resource->limit > limit) {
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resource->limit = limit;
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}
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return resource;
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}
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/**
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* Given a device and an index, read the size of the BAR for that register.
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*
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* @param dev Pointer to the device structure.
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* @param index Address of the PCI configuration register.
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*/
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static void pci_get_rom_resource(struct device *dev, unsigned long index)
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{
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struct resource *resource;
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unsigned long value;
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resource_t moving;
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if ((dev->on_mainboard) && (dev->rom_address == 0)) {
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/* Skip it if rom_address is not set in the MB Config.lb. */
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return;
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}
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/* Initialize the resources to nothing. */
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resource = new_resource(dev, index);
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/* Get the initial value. */
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value = pci_read_config32(dev, index);
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/* See which bits move. */
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moving = pci_moving_config32(dev, index);
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/* Clear the Enable bit. */
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moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
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/* Find the resource constraints.
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* Start by finding the bits that move. From there:
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* - Size is the least significant bit of the bits that move.
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* - Limit is all of the bits that move plus all of the lower bits.
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* See PCI Spec 6.2.5.1.
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*/
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if (moving) {
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resource->size = 1;
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resource->align = resource->gran = 0;
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while (!(moving & resource->size)) {
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resource->size <<= 1;
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resource->align += 1;
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resource->gran += 1;
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}
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resource->limit = moving | (resource->size - 1);
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resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
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} else {
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if (value != 0) {
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printk_debug
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("%s register %02lx(%08lx), read-only ignoring it\n",
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dev_path(dev), index, value);
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}
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resource->flags = 0;
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}
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/* For on board device with embedded ROM image, the ROM image is at
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* fixed address specified in the Config.lb, the dev->rom_address is
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* inited by driver_pci_onboard_ops::enable_dev() */
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if ((dev->on_mainboard) && (dev->rom_address != 0)) {
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resource->base = dev->rom_address;
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/* The resource allocator needs the size to be non-zero. */
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resource->size = 0x100;
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resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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compact_resources(dev);
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}
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/**
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* Read the base address registers for a given device.
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*
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* @param dev Pointer to the dev structure.
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* @param howmany How many registers to read (6 for device, 2 for bridge).
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*/
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static void pci_read_bases(struct device *dev, unsigned int howmany)
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{
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unsigned long index;
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for (index = PCI_BASE_ADDRESS_0;
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(index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
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struct resource *resource;
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resource = pci_get_resource(dev, index);
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index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
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}
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compact_resources(dev);
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}
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static void pci_record_bridge_resource(struct device *dev, resource_t moving,
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unsigned index, unsigned long type)
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{
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/* Initialize the constraints on the current bus. */
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struct resource *resource;
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resource = NULL;
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if (moving) {
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unsigned long gran;
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resource_t step;
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resource = new_resource(dev, index);
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resource->size = 0;
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gran = 0;
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step = 1;
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while ((moving & step) == 0) {
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gran += 1;
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step <<= 1;
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}
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resource->gran = gran;
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resource->align = gran;
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resource->limit = moving | (step - 1);
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resource->flags = type | IORESOURCE_PCI_BRIDGE |
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IORESOURCE_BRIDGE;
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}
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return;
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}
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static void pci_bridge_read_bases(struct device *dev)
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{
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resource_t moving_base, moving_limit, moving;
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/* See if the bridge I/O resources are implemented. */
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moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8;
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moving_base |=
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((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
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moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
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moving_limit |=
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((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
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moving = moving_base & moving_limit;
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/* Initialize the I/O space constraints on the current bus. */
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pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO);
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/* See if the bridge prefmem resources are implemented. */
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moving_base =
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((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
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moving_base |=
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((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) <<
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32;
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moving_limit =
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((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) <<
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16;
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moving_limit |=
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((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) <<
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32;
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moving = moving_base & moving_limit;
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/* Initialize the prefetchable memory constraints on the current bus. */
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pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
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IORESOURCE_MEM | IORESOURCE_PREFETCH);
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/* See if the bridge mem resources are implemented. */
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moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
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moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
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moving = moving_base & moving_limit;
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/* Initialize the memory resources on the current bus. */
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pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
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IORESOURCE_MEM);
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compact_resources(dev);
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}
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void pci_dev_read_resources(struct device *dev)
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{
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pci_read_bases(dev, 6);
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pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
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}
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void pci_bus_read_resources(struct device *dev)
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{
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pci_bridge_read_bases(dev);
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pci_read_bases(dev, 2);
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pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
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}
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void pci_domain_read_resources(struct device *dev)
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{
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struct resource *res;
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/* Initialize the system-wide I/O space constraints. */
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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res->limit = 0xffffUL;
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res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED;
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/* Initialize the system-wide memory resources constraints. */
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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res->limit = 0xffffffffULL;
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res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED;
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}
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static void pci_set_resource(struct device *dev, struct resource *resource)
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{
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resource_t base, end;
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/* Make certain the resource has actually been assigned a value. */
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if (!(resource->flags & IORESOURCE_ASSIGNED)) {
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printk_err("ERROR: %s %02lx %s size: 0x%010llx not assigned\n",
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dev_path(dev), resource->index,
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resource_type(resource), resource->size);
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return;
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}
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|
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/* If I have already stored this resource don't worry about it. */
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if (resource->flags & IORESOURCE_STORED) {
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return;
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}
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|
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/* If the resource is subtractive don't worry about it. */
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if (resource->flags & IORESOURCE_SUBTRACTIVE) {
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return;
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}
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|
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/* Only handle PCI memory and I/O resources for now. */
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if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
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return;
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|
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/* Enable the resources in the command register. */
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if (resource->size) {
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if (resource->flags & IORESOURCE_MEM) {
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dev->command |= PCI_COMMAND_MEMORY;
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}
|
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if (resource->flags & IORESOURCE_IO) {
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dev->command |= PCI_COMMAND_IO;
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}
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if (resource->flags & IORESOURCE_PCI_BRIDGE) {
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dev->command |= PCI_COMMAND_MASTER;
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}
|
|
}
|
|
/* Get the base address. */
|
|
base = resource->base;
|
|
|
|
/* Get the end. */
|
|
end = resource_end(resource);
|
|
|
|
/* Now store the resource. */
|
|
resource->flags |= IORESOURCE_STORED;
|
|
|
|
/* PCI Bridges have no enable bit. They are disabled if the base of
|
|
* the range is greater than the limit. If the size is zero, disable
|
|
* by setting the base = limit and end = limit - 2^gran.
|
|
*/
|
|
if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
|
|
base = resource->limit;
|
|
end = resource->limit - (1 << resource->gran);
|
|
resource->base = base;
|
|
}
|
|
|
|
if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
|
|
unsigned long base_lo, base_hi;
|
|
/* Some chipsets allow us to set/clear the I/O bit
|
|
* (e.g. VIA 82c686a). So set it to be safe.
|
|
*/
|
|
base_lo = base & 0xffffffff;
|
|
base_hi = (base >> 32) & 0xffffffff;
|
|
if (resource->flags & IORESOURCE_IO) {
|
|
base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
|
|
}
|
|
pci_write_config32(dev, resource->index, base_lo);
|
|
if (resource->flags & IORESOURCE_PCI64) {
|
|
pci_write_config32(dev, resource->index + 4, base_hi);
|
|
}
|
|
} else if (resource->index == PCI_IO_BASE) {
|
|
/* Set the I/O ranges. */
|
|
pci_write_config8(dev, PCI_IO_BASE, base >> 8);
|
|
pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
|
|
pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
|
|
pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
|
|
} else if (resource->index == PCI_MEMORY_BASE) {
|
|
/* Set the memory range. */
|
|
pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
|
|
pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
|
|
} else if (resource->index == PCI_PREF_MEMORY_BASE) {
|
|
/* Set the prefetchable memory range. */
|
|
pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
|
|
pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
|
|
pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
|
|
pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
|
|
} else {
|
|
/* Don't let me think I stored the resource. */
|
|
resource->flags &= ~IORESOURCE_STORED;
|
|
printk_err("ERROR: invalid resource->index %lx\n",
|
|
resource->index);
|
|
}
|
|
report_resource_stored(dev, resource, "");
|
|
return;
|
|
}
|
|
|
|
void pci_dev_set_resources(struct device *dev)
|
|
{
|
|
struct resource *resource, *last;
|
|
unsigned link;
|
|
u8 line;
|
|
|
|
last = &dev->resource[dev->resources];
|
|
|
|
for (resource = &dev->resource[0]; resource < last; resource++) {
|
|
pci_set_resource(dev, resource);
|
|
}
|
|
for (link = 0; link < dev->links; link++) {
|
|
struct bus *bus;
|
|
bus = &dev->link[link];
|
|
if (bus->children) {
|
|
assign_resources(bus);
|
|
}
|
|
}
|
|
|
|
/* Set a default latency timer. */
|
|
pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
|
|
|
|
/* Set a default secondary latency timer. */
|
|
if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
|
|
pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
|
|
}
|
|
|
|
/* Zero the IRQ settings. */
|
|
line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
|
|
if (line) {
|
|
pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
|
|
}
|
|
/* Set the cache line size, so far 64 bytes is good for everyone. */
|
|
pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
|
|
}
|
|
|
|
void pci_dev_enable_resources(struct device *dev)
|
|
{
|
|
const struct pci_operations *ops;
|
|
u16 command;
|
|
|
|
/* Set the subsystem vendor and device id for mainboard devices. */
|
|
ops = ops_pci(dev);
|
|
if (dev->on_mainboard && ops && ops->set_subsystem) {
|
|
printk_debug("%s subsystem <- %02x/%02x\n",
|
|
dev_path(dev),
|
|
CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
|
|
CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
|
|
ops->set_subsystem(dev,
|
|
CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
|
|
CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
|
|
}
|
|
command = pci_read_config16(dev, PCI_COMMAND);
|
|
command |= dev->command;
|
|
/* v3 has
|
|
* command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check.
|
|
*/
|
|
printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
|
|
pci_write_config16(dev, PCI_COMMAND, command);
|
|
}
|
|
|
|
void pci_bus_enable_resources(struct device *dev)
|
|
{
|
|
u16 ctrl;
|
|
|
|
/* Enable I/O in command register if there is VGA card
|
|
* connected with (even it does not claim I/O resource).
|
|
*/
|
|
if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
|
|
dev->command |= PCI_COMMAND_IO;
|
|
ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
|
|
ctrl |= dev->link[0].bridge_ctrl;
|
|
ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */
|
|
printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
|
|
pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
|
|
|
|
pci_dev_enable_resources(dev);
|
|
enable_childrens_resources(dev);
|
|
}
|
|
|
|
void pci_bus_reset(struct bus *bus)
|
|
{
|
|
unsigned ctl;
|
|
ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
|
|
ctl |= PCI_BRIDGE_CTL_BUS_RESET;
|
|
pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
|
|
mdelay(10);
|
|
ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
|
|
pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
|
|
delay(1);
|
|
}
|
|
|
|
void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
|
|
{
|
|
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
|
((device & 0xffff) << 16) | (vendor & 0xffff));
|
|
}
|
|
|
|
/** default handler: only runs the relevant pci bios. */
|
|
void pci_dev_init(struct device *dev)
|
|
{
|
|
#if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
|
|
void run_bios(struct device *dev, unsigned long addr);
|
|
struct rom_header *rom, *ram;
|
|
|
|
if (CONFIG_PCI_ROM_RUN != 1 && /* Only execute VGA ROMs. */
|
|
((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))
|
|
return;
|
|
|
|
if (CONFIG_VGA_ROM_RUN != 1 && /* Only execute non-VGA ROMs. */
|
|
((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
|
|
return;
|
|
|
|
rom = pci_rom_probe(dev);
|
|
if (rom == NULL)
|
|
return;
|
|
|
|
ram = pci_rom_load(dev, rom);
|
|
if (ram == NULL)
|
|
return;
|
|
|
|
run_bios(dev, (unsigned long)ram);
|
|
|
|
#if CONFIG_CONSOLE_VGA == 1
|
|
if ((dev->class>>8) == PCI_CLASS_DISPLAY_VGA)
|
|
vga_console_init();
|
|
#endif /* CONFIG_CONSOLE_VGA */
|
|
#endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
|
|
}
|
|
|
|
/** Default device operation for PCI devices */
|
|
static struct pci_operations pci_dev_ops_pci = {
|
|
.set_subsystem = pci_dev_set_subsystem,
|
|
};
|
|
|
|
struct device_operations default_pci_ops_dev = {
|
|
.read_resources = pci_dev_read_resources,
|
|
.set_resources = pci_dev_set_resources,
|
|
.enable_resources = pci_dev_enable_resources,
|
|
.init = pci_dev_init,
|
|
.scan_bus = 0,
|
|
.enable = 0,
|
|
.ops_pci = &pci_dev_ops_pci,
|
|
};
|
|
|
|
/** Default device operations for PCI bridges */
|
|
static struct pci_operations pci_bus_ops_pci = {
|
|
.set_subsystem = 0,
|
|
};
|
|
|
|
struct device_operations default_pci_ops_bus = {
|
|
.read_resources = pci_bus_read_resources,
|
|
.set_resources = pci_dev_set_resources,
|
|
.enable_resources = pci_bus_enable_resources,
|
|
.init = 0,
|
|
.scan_bus = pci_scan_bridge,
|
|
.enable = 0,
|
|
.reset_bus = pci_bus_reset,
|
|
.ops_pci = &pci_bus_ops_pci,
|
|
};
|
|
|
|
/**
|
|
* @brief Detect the type of downstream bridge
|
|
*
|
|
* This function is a heuristic to detect which type of bus is downstream
|
|
* of a PCI-to-PCI bridge. This functions by looking for various capability
|
|
* blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and
|
|
* Hypertransport all seem to have appropriate capabilities.
|
|
*
|
|
* When only a PCI-Express capability is found the type
|
|
* is examined to see which type of bridge we have.
|
|
*
|
|
* @param dev Pointer to the device structure of the bridge.
|
|
* @return Appropriate bridge operations.
|
|
*/
|
|
static struct device_operations *get_pci_bridge_ops(device_t dev)
|
|
{
|
|
unsigned pos;
|
|
|
|
#if CONFIG_PCIX_PLUGIN_SUPPORT == 1
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
|
|
if (pos) {
|
|
printk_debug("%s subordinate bus PCI-X\n", dev_path(dev));
|
|
return &default_pcix_ops_bus;
|
|
}
|
|
#endif
|
|
#if CONFIG_AGP_PLUGIN_SUPPORT == 1
|
|
/* How do I detect an PCI to AGP bridge? */
|
|
#endif
|
|
#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
|
|
pos = 0;
|
|
while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
|
|
unsigned flags;
|
|
flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
|
|
if ((flags >> 13) == 1) {
|
|
/* Host or Secondary Interface */
|
|
printk_debug("%s subordinate bus Hypertransport\n",
|
|
dev_path(dev));
|
|
return &default_ht_ops_bus;
|
|
}
|
|
}
|
|
#endif
|
|
#if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
|
|
if (pos) {
|
|
unsigned flags;
|
|
flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
|
|
switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
|
|
case PCI_EXP_TYPE_ROOT_PORT:
|
|
case PCI_EXP_TYPE_UPSTREAM:
|
|
case PCI_EXP_TYPE_DOWNSTREAM:
|
|
printk_debug("%s subordinate bus PCI Express\n",
|
|
dev_path(dev));
|
|
return &default_pciexp_ops_bus;
|
|
case PCI_EXP_TYPE_PCI_BRIDGE:
|
|
printk_debug("%s subordinate PCI\n", dev_path(dev));
|
|
return &default_pci_ops_bus;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
#endif
|
|
return &default_pci_ops_bus;
|
|
}
|
|
|
|
/**
|
|
* Set up PCI device operation. Check if it already has a driver. If not, use
|
|
* find_device_operations, or set to a default based on type.
|
|
*
|
|
* @param dev Pointer to the device whose pci_ops you want to set.
|
|
* @see pci_drivers
|
|
*/
|
|
static void set_pci_ops(struct device *dev)
|
|
{
|
|
struct pci_driver *driver;
|
|
if (dev->ops) {
|
|
return;
|
|
}
|
|
|
|
/* Look through the list of setup drivers and find one for
|
|
* this PCI device.
|
|
*/
|
|
for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
|
|
if ((driver->vendor == dev->vendor) &&
|
|
(driver->device == dev->device)) {
|
|
dev->ops = (struct device_operations *)driver->ops;
|
|
printk_spew("%s [%04x/%04x] %sops\n",
|
|
dev_path(dev),
|
|
driver->vendor, driver->device,
|
|
(driver->ops->scan_bus ? "bus " : ""));
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* If I don't have a specific driver use the default operations */
|
|
switch (dev->hdr_type & 0x7f) { /* header type */
|
|
case PCI_HEADER_TYPE_NORMAL: /* standard header */
|
|
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
|
|
goto bad;
|
|
dev->ops = &default_pci_ops_dev;
|
|
break;
|
|
case PCI_HEADER_TYPE_BRIDGE:
|
|
if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
|
|
goto bad;
|
|
dev->ops = get_pci_bridge_ops(dev);
|
|
break;
|
|
#if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
|
|
case PCI_HEADER_TYPE_CARDBUS:
|
|
dev->ops = &default_cardbus_ops_bus;
|
|
break;
|
|
#endif
|
|
default:
|
|
bad:
|
|
if (dev->enabled) {
|
|
printk_err("%s [%04x/%04x/%06x] has unknown header "
|
|
"type %02x, ignoring.\n",
|
|
dev_path(dev),
|
|
dev->vendor, dev->device,
|
|
dev->class >> 8, dev->hdr_type);
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
/**
|
|
* @brief See if we have already allocated a device structure for a given devfn.
|
|
*
|
|
* Given a linked list of PCI device structures and a devfn number, find the
|
|
* device structure correspond to the devfn, if present. This function also
|
|
* removes the device structure from the linked list.
|
|
*
|
|
* @param list The device structure list.
|
|
* @param devfn A device/function number.
|
|
*
|
|
* @return Pointer to the device structure found or NULL if we have not
|
|
* allocated a device for this devfn yet.
|
|
*/
|
|
static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
|
|
{
|
|
struct device *dev;
|
|
dev = 0;
|
|
for (; *list; list = &(*list)->sibling) {
|
|
if ((*list)->path.type != DEVICE_PATH_PCI) {
|
|
printk_err("child %s not a pci device\n",
|
|
dev_path(*list));
|
|
continue;
|
|
}
|
|
if ((*list)->path.pci.devfn == devfn) {
|
|
/* Unlink from the list. */
|
|
dev = *list;
|
|
*list = (*list)->sibling;
|
|
dev->sibling = NULL;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Just like alloc_dev() add the device to the list of devices on the
|
|
* bus. When the list of devices was formed we removed all of the
|
|
* parents children, and now we are interleaving static and dynamic
|
|
* devices in order on the bus.
|
|
*/
|
|
if (dev) {
|
|
struct device *child;
|
|
/* Find the last child of our parent. */
|
|
for (child = dev->bus->children; child && child->sibling;) {
|
|
child = child->sibling;
|
|
}
|
|
/* Place the device on the list of children of its parent. */
|
|
if (child) {
|
|
child->sibling = dev;
|
|
} else {
|
|
dev->bus->children = dev;
|
|
}
|
|
}
|
|
|
|
return dev;
|
|
}
|
|
|
|
/**
|
|
* @brief Scan a PCI bus.
|
|
*
|
|
* Determine the existence of a given PCI device. Allocate a new struct device
|
|
* if dev==NULL was passed in and the device exists in hardware.
|
|
*
|
|
* @param bus pointer to the bus structure
|
|
* @param devfn to look at
|
|
*
|
|
* @return The device structure for hte device (if found)
|
|
* or the NULL if no device is found.
|
|
*/
|
|
device_t pci_probe_dev(device_t dev, struct bus * bus, unsigned devfn)
|
|
{
|
|
u32 id, class;
|
|
u8 hdr_type;
|
|
|
|
/* Detect if a device is present. */
|
|
if (!dev) {
|
|
struct device dummy;
|
|
dummy.bus = bus;
|
|
dummy.path.type = DEVICE_PATH_PCI;
|
|
dummy.path.pci.devfn = devfn;
|
|
id = pci_read_config32(&dummy, PCI_VENDOR_ID);
|
|
/* Have we found something?
|
|
* Some broken boards return 0 if a slot is empty.
|
|
*/
|
|
if ((id == 0xffffffff) || (id == 0x00000000) ||
|
|
(id == 0x0000ffff) || (id == 0xffff0000)) {
|
|
printk_spew("%s, bad id 0x%x\n", dev_path(&dummy), id);
|
|
return NULL;
|
|
}
|
|
dev = alloc_dev(bus, &dummy.path);
|
|
} else {
|
|
/* Enable/disable the device. Once we have found the device-
|
|
* specific operations this operations we will disable the
|
|
* device with those as well.
|
|
*
|
|
* This is geared toward devices that have subfunctions
|
|
* that do not show up by default.
|
|
*
|
|
* If a device is a stuff option on the motherboard
|
|
* it may be absent and enable_dev() must cope.
|
|
*/
|
|
/* Run the magic enable sequence for the device. */
|
|
if (dev->chip_ops && dev->chip_ops->enable_dev) {
|
|
dev->chip_ops->enable_dev(dev);
|
|
}
|
|
/* Now read the vendor and device ID. */
|
|
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
|
|
|
/* If the device does not have a PCI ID disable it. Possibly
|
|
* this is because we have already disabled the device. But
|
|
* this also handles optional devices that may not always
|
|
* show up.
|
|
*/
|
|
/* If the chain is fully enumerated quit */
|
|
if ((id == 0xffffffff) || (id == 0x00000000) ||
|
|
(id == 0x0000ffff) || (id == 0xffff0000)) {
|
|
if (dev->enabled) {
|
|
printk_info("Disabling static device: %s\n",
|
|
dev_path(dev));
|
|
dev->enabled = 0;
|
|
}
|
|
return dev;
|
|
}
|
|
}
|
|
/* Read the rest of the PCI configuration information. */
|
|
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
|
|
class = pci_read_config32(dev, PCI_CLASS_REVISION);
|
|
|
|
/* Store the interesting information in the device structure. */
|
|
dev->vendor = id & 0xffff;
|
|
dev->device = (id >> 16) & 0xffff;
|
|
dev->hdr_type = hdr_type;
|
|
|
|
/* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
|
|
dev->class = class >> 8;
|
|
|
|
/* Architectural/System devices always need to be bus masters. */
|
|
if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
|
|
dev->command |= PCI_COMMAND_MASTER;
|
|
}
|
|
/* Look at the vendor and device ID, or at least the header type and
|
|
* class and figure out which set of configuration methods to use.
|
|
* Unless we already have some PCI ops.
|
|
*/
|
|
set_pci_ops(dev);
|
|
|
|
/* Now run the magic enable/disable sequence for the device. */
|
|
if (dev->ops && dev->ops->enable) {
|
|
dev->ops->enable(dev);
|
|
}
|
|
|
|
/* Display the device. */
|
|
printk_debug("%s [%04x/%04x] %s%s\n",
|
|
dev_path(dev),
|
|
dev->vendor, dev->device,
|
|
dev->enabled ? "enabled" : "disabled",
|
|
dev->ops ? "" : " No operations");
|
|
|
|
return dev;
|
|
}
|
|
|
|
/**
|
|
* @brief Scan a PCI bus.
|
|
*
|
|
* Determine the existence of devices and bridges on a PCI bus. If there are
|
|
* bridges on the bus, recursively scan the buses behind the bridges.
|
|
*
|
|
* This function is the default scan_bus() method for the root device
|
|
* 'dev_root'.
|
|
*
|
|
* @param bus pointer to the bus structure
|
|
* @param min_devfn minimum devfn to look at in the scan usually 0x00
|
|
* @param max_devfn maximum devfn to look at in the scan usually 0xff
|
|
* @param max current bus number
|
|
*
|
|
* @return The maximum bus number found, after scanning all subordinate busses
|
|
*/
|
|
unsigned int pci_scan_bus(struct bus *bus,
|
|
unsigned min_devfn, unsigned max_devfn,
|
|
unsigned int max)
|
|
{
|
|
unsigned int devfn;
|
|
struct device *old_devices;
|
|
struct device *child;
|
|
|
|
#if CONFIG_PCI_BUS_SEGN_BITS
|
|
printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n",
|
|
bus->secondary >> 8, bus->secondary & 0xff);
|
|
#else
|
|
printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary);
|
|
#endif
|
|
|
|
old_devices = bus->children;
|
|
bus->children = NULL;
|
|
|
|
post_code(0x24);
|
|
/* Probe all devices/functions on this bus with some optimization for
|
|
* non-existence and single function devices.
|
|
*/
|
|
for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
|
|
struct device *dev;
|
|
|
|
/* First thing setup the device structure */
|
|
dev = pci_scan_get_dev(&old_devices, devfn);
|
|
|
|
/* See if a device is present and setup the device structure. */
|
|
dev = pci_probe_dev(dev, bus, devfn);
|
|
|
|
/* If this is not a multi function device, or the device is
|
|
* not present don't waste time probing another function.
|
|
* Skip to next device.
|
|
*/
|
|
if ((PCI_FUNC(devfn) == 0x00) &&
|
|
(!dev
|
|
|| (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) {
|
|
devfn += 0x07;
|
|
}
|
|
}
|
|
post_code(0x25);
|
|
|
|
/* Warn if any leftover static devices are are found.
|
|
* There's probably a problem in the Config.lb.
|
|
*/
|
|
if (old_devices) {
|
|
device_t left;
|
|
printk_warning("PCI: Left over static devices:\n");
|
|
for (left = old_devices; left; left = left->sibling) {
|
|
printk_warning("%s\n", dev_path(left));
|
|
}
|
|
printk_warning("PCI: Check your mainboard Config.lb.\n");
|
|
}
|
|
|
|
/* For all children that implement scan_bus() (i.e. bridges)
|
|
* scan the bus behind that child.
|
|
*/
|
|
for (child = bus->children; child; child = child->sibling) {
|
|
max = scan_bus(child, max);
|
|
}
|
|
|
|
/* We've scanned the bus and so we know all about what's on the other
|
|
* side of any bridges that may be on this bus plus any devices.
|
|
* Return how far we've got finding sub-buses.
|
|
*/
|
|
printk_debug("PCI: pci_scan_bus returning with max=%03x\n", max);
|
|
post_code(0x55);
|
|
return max;
|
|
}
|
|
|
|
/**
|
|
* @brief Scan a PCI bridge and the buses behind the bridge.
|
|
*
|
|
* Determine the existence of buses behind the bridge. Set up the bridge
|
|
* according to the result of the scan.
|
|
*
|
|
* This function is the default scan_bus() method for PCI bridge devices.
|
|
*
|
|
* @param dev Pointer to the bridge device.
|
|
* @param max The highest bus number assigned up to now.
|
|
* @return The maximum bus number found, after scanning all subordinate buses.
|
|
*/
|
|
unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
|
|
unsigned int (*do_scan_bus) (struct bus * bus,
|
|
unsigned min_devfn,
|
|
unsigned max_devfn,
|
|
unsigned int max))
|
|
{
|
|
struct bus *bus;
|
|
u32 buses;
|
|
u16 cr;
|
|
|
|
printk_spew("%s for %s\n", __func__, dev_path(dev));
|
|
|
|
bus = &dev->link[0];
|
|
bus->dev = dev;
|
|
dev->links = 1;
|
|
|
|
/* Set up the primary, secondary and subordinate bus numbers. We have
|
|
* no idea how many buses are behind this bridge yet, so we set the
|
|
* subordinate bus number to 0xff for the moment.
|
|
*/
|
|
bus->secondary = ++max;
|
|
bus->subordinate = 0xff;
|
|
|
|
/* Clear all status bits and turn off memory, I/O and master enables. */
|
|
cr = pci_read_config16(dev, PCI_COMMAND);
|
|
pci_write_config16(dev, PCI_COMMAND, 0x0000);
|
|
pci_write_config16(dev, PCI_STATUS, 0xffff);
|
|
|
|
/* Read the existing primary/secondary/subordinate bus
|
|
* number configuration.
|
|
*/
|
|
buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
|
|
|
|
/* Configure the bus numbers for this bridge: the configuration
|
|
* transactions will not be propagated by the bridge if it is not
|
|
* correctly configured.
|
|
*/
|
|
buses &= 0xff000000;
|
|
buses |= (((unsigned int)(dev->bus->secondary) << 0) |
|
|
((unsigned int)(bus->secondary) << 8) |
|
|
((unsigned int)(bus->subordinate) << 16));
|
|
pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
|
|
|
|
/* Now we can scan all subordinate buses
|
|
* i.e. the bus behind the bridge.
|
|
*/
|
|
max = do_scan_bus(bus, 0x00, 0xff, max);
|
|
|
|
/* We know the number of buses behind this bridge. Set the subordinate
|
|
* bus number to its real value.
|
|
*/
|
|
bus->subordinate = max;
|
|
buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16);
|
|
pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
|
|
pci_write_config16(dev, PCI_COMMAND, cr);
|
|
|
|
printk_spew("%s returns max %d\n", __func__, max);
|
|
return max;
|
|
}
|
|
|
|
/**
|
|
* @brief Scan a PCI bridge and the buses behind the bridge.
|
|
*
|
|
* Determine the existence of buses behind the bridge. Set up the bridge
|
|
* according to the result of the scan.
|
|
*
|
|
* This function is the default scan_bus() method for PCI bridge devices.
|
|
*
|
|
* @param dev Pointer to the bridge device.
|
|
* @param max The highest bus number assigned up to now.
|
|
* @return The maximum bus number found, after scanning all subordinate buses.
|
|
*/
|
|
unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
|
|
{
|
|
return do_pci_scan_bridge(dev, max, pci_scan_bus);
|
|
}
|
|
|
|
/**
|
|
* @brief Scan a PCI domain.
|
|
*
|
|
* This function is the default scan_bus() method for PCI domains.
|
|
*
|
|
* @param dev pointer to the domain
|
|
* @param max the highest bus number assgined up to now
|
|
*
|
|
* @return The maximum bus number found, after scanning all subordinate busses
|
|
*/
|
|
unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
|
|
{
|
|
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
|
|
return max;
|
|
}
|
|
|
|
#if CONFIG_PC80_SYSTEM == 1
|
|
/**
|
|
*
|
|
* @brief Assign IRQ numbers
|
|
*
|
|
* This function assigns IRQs for all functions contained within the indicated
|
|
* device address. If the device does not exist or does not require interrupts
|
|
* then this function has no effect.
|
|
*
|
|
* This function should be called for each PCI slot in your system.
|
|
*
|
|
* @param bus
|
|
* @param slot
|
|
* @param pIntAtoD is an array of IRQ #s that are assigned to PINTA through
|
|
* PINTD of this slot. The particular irq #s that are passed in
|
|
* depend on the routing inside your southbridge and on your
|
|
* motherboard.
|
|
*/
|
|
void pci_assign_irqs(unsigned bus, unsigned slot,
|
|
const unsigned char pIntAtoD[4])
|
|
{
|
|
unsigned int funct;
|
|
device_t pdev;
|
|
u8 line;
|
|
u8 irq;
|
|
|
|
/* Each slot may contain up to eight functions */
|
|
for (funct = 0; funct < 8; funct++) {
|
|
pdev = dev_find_slot(bus, (slot << 3) + funct);
|
|
|
|
if (!pdev)
|
|
continue;
|
|
|
|
line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
|
|
|
|
// PCI spec says all values except 1..4 are reserved.
|
|
if ((line < 1) || (line > 4))
|
|
continue;
|
|
|
|
irq = pIntAtoD[line - 1];
|
|
|
|
printk_debug("Assigning IRQ %d to %d:%x.%d\n",
|
|
irq, bus, slot, funct);
|
|
|
|
pci_write_config8(pdev, PCI_INTERRUPT_LINE,
|
|
pIntAtoD[line - 1]);
|
|
|
|
#ifdef PARANOID_IRQ_ASSIGNMENTS
|
|
irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
|
|
printk_debug(" Readback = %d\n", irq);
|
|
#endif
|
|
|
|
// Change to level triggered
|
|
i8259_configure_irq_trigger(pIntAtoD[line - 1], IRQ_LEVEL_TRIGGERED);
|
|
}
|
|
}
|
|
#endif
|
|
|