6e3728bb12
Per a conversation with Stefan, these chip-dependent files are moved to the src tree, in the manner of other chips (north and southbridge). Change-Id: I12645ba05eb241eda200ed06cb633541a6a98119 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Reviewed-on: http://review.coreboot.org/1925 Tested-by: build bot (Jenkins)
137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
/*
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* (C) Copyright 2012 Samsung Electronics
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* Register map for Exynos5 FIMD
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __EXYNOS5_FIMD_H__
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#define __EXYNOS5_FIMD_H__
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/* FIMD register map */
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struct exynos5_fimd {
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/* This is an incomplete list. Add registers as and when required */
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unsigned int vidcon0;
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unsigned char res1[0x1c];
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unsigned int wincon0;
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unsigned int wincon1;
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unsigned int wincon2;
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unsigned int wincon3;
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unsigned int wincon4;
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unsigned int shadowcon;
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unsigned char res2[0x8];
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unsigned int vidosd0a;
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unsigned int vidosd0b;
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unsigned int vidosd0c;
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unsigned char res3[0x54];
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unsigned int vidw00add0b0;
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unsigned char res4[0x2c];
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unsigned int vidw00add1b0;
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unsigned char res5[0x2c];
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unsigned int vidw00add2;
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unsigned char res6[0x3c];
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unsigned int w1keycon0;
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unsigned int w1keycon1;
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unsigned int w2keycon0;
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unsigned int w2keycon1;
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unsigned int w3keycon0;
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unsigned int w3keycon1;
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unsigned int w4keycon0;
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unsigned int w4keycon1;
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unsigned char res7[0x20];
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unsigned int win0map;
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unsigned char res8[0xdc];
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unsigned int blendcon;
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unsigned char res9[0x18];
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unsigned int dpclkcon;
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};
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#define W0_SHADOW_PROTECT (0x1 << 10)
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#define COMPKEY_F 0xffffff
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#define ENVID_F_ON (0x1 << 0)
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#define ENVID_ON (0x1 << 1)
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#define CLKVAL_F 0xb
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#define CLKVAL_F_OFFSET 6
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/*
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* Structure containing display panel specific data for FIMD
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*/
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struct exynos5_fimd_panel {
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unsigned int is_dp:1; /* Display Panel interface is eDP */
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unsigned int is_mipi:1; /* Display Panel interface is MIPI */
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unsigned int fixvclk:2; /* VCLK hold scheme at data underflow */
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/*
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* Polarity of the VCLK active edge
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* 0-falling
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* 1-rising
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*/
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unsigned int ivclk:1;
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unsigned int clkval_f; /* Divider to create pixel clock */
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unsigned int upper_margin; /* Vertical Backporch */
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unsigned int lower_margin; /* Vertical frontporch */
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unsigned int vsync; /* Vertical Sync Pulse Width */
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unsigned int left_margin; /* Horizantal Backporch */
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unsigned int right_margin; /* Horizontal Frontporch */
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unsigned int hsync; /* Horizontal Sync Pulse Width */
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unsigned int xres; /* X Resolution */
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unsigned int yres; /* Y Resopultion */
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};
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/* LCDIF Register Map */
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struct exynos5_disp_ctrl {
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unsigned int vidout_con;
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unsigned int vidcon1;
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unsigned char res1[0x8];
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unsigned int vidtcon0;
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unsigned int vidtcon1;
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unsigned int vidtcon2;
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unsigned int vidtcon3;
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unsigned char res2[0x184];
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unsigned int trigcon;
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};
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#define VCLK_RISING_EDGE (1 << 7)
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#define VCLK_RUNNING (1 << 9)
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#define CHANNEL0_EN (1 << 0)
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#define VSYNC_PULSE_WIDTH_VAL 0x3
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#define VSYNC_PULSE_WIDTH_OFFSET 0
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#define V_FRONT_PORCH_VAL 0x3
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#define V_FRONT_PORCH_OFFSET 8
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#define V_BACK_PORCH_VAL 0x3
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#define V_BACK_PORCH_OFFSET 16
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#define HSYNC_PULSE_WIDTH_VAL 0x3
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#define HSYNC_PULSE_WIDTH_OFFSET 0
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#define H_FRONT_PORCH_VAL 0x3
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#define H_FRONT_PORCH_OFFSET 8
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#define H_BACK_PORCH_VAL 0x3
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#define H_BACK_PORCH_OFFSET 16
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#define HOZVAL_OFFSET 0
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#define LINEVAL_OFFSET 11
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#define BPPMODE_F_RGB_16BIT_565 0x5
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#define BPPMODE_F_OFFSET 2
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#define ENWIN_F_ENABLE (1 << 0)
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#define HALF_WORD_SWAP_EN (1 << 16)
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#define OSD_RIGHTBOTX_F_OFFSET 11
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#define OSD_RIGHTBOTY_F_OFFSET 0
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#endif
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