44e89af6e6
We had two ways to configure the serial IRQ mode. One time in the devicetree for FSP and one time through Kconfig for coreboot. We'll use `enum serirq_mode` from soc/intel/common/ as a devicetree option instead. As the default is `quiet mode` here and that is the most common mode, this saves us a lot of lines. In four cases kblrvp8, 11 and librem 13v2, 15v3, we had conflicting settings in devicetree and Kconfig. We'll maintain the `continuous` selection, although it might be that coreboot overrode this earlier on the kblrvps. Note: A lot of Google boards have serial IRQ enabled, while the pin seems to be unconnected? Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
130 lines
3.4 KiB
C
130 lines
3.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015-2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "chip.h"
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <pc80/isa-dma.h>
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#include <pc80/i8259.h>
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <intelblocks/itss.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <reg_script.h>
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#include <soc/iomap.h>
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#include <soc/pcr_ids.h>
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#include <soc/intel/common/block/lpc/lpc_def.h>
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/**
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PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF
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**/
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static const struct lpc_mmio_range skl_lpc_fixed_mmio_ranges[] = {
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{ PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
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{ 0, 0 }
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};
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const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
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{
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return skl_lpc_fixed_mmio_ranges;
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}
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static void pch_enable_ioapic(struct device *dev)
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{
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u32 reg32;
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/* PCH-LP has 120 redirection entries */
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const int redir_entries = 120;
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set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
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/* affirm full set of redirection table entries ("write once") */
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reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
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reg32 &= ~0x00ff0000;
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reg32 |= (redir_entries - 1) << 16;
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io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
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/*
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* Select Boot Configuration register (0x03) and
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* use Processor System Bus (0x01) to deliver interrupts.
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*/
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io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
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}
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void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
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{
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const config_t *config = dev->chip_info;
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gen_io_dec[0] = config->gen1_dec;
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gen_io_dec[1] = config->gen2_dec;
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gen_io_dec[2] = config->gen3_dec;
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gen_io_dec[3] = config->gen4_dec;
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}
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void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
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{
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/* Mirror these same settings in DMI PCR */
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
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}
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static const struct reg_script pch_misc_init_script[] = {
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/* Setup NMI on errors, disable SERR */
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REG_IO_RMW8(0x61, ~0xf0, (1 << 2)),
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/* Disable NMI sources */
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REG_IO_OR8(0x70, (1 << 7)),
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/* Enable BIOS updates outside of SMM */
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REG_PCI_RMW8(0xdc, ~(1 << 5), 0),
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REG_SCRIPT_END
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};
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static void clock_gate_8254(struct device *dev)
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{
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const config_t *config = dev->chip_info;
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if (!config->clock_gate_8254)
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return;
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itss_clock_gate_8254();
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}
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void lpc_soc_init(struct device *dev)
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{
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const config_t *const config = dev->chip_info;
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/* Legacy initialization */
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isa_dma_init();
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reg_script_run_on_dev(PCH_DEV_LPC, pch_misc_init_script);
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/* Enable CLKRUN_EN for power gating LPC */
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lpc_enable_pci_clk_cntl();
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/* Set LPC Serial IRQ mode */
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lpc_set_serirq_mode(config->serirq_mode);
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/* Interrupt configuration */
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pch_enable_ioapic(dev);
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soc_pch_pirq_init(dev);
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setup_i8259();
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i8259_configure_irq_trigger(9, 1);
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clock_gate_8254(dev);
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}
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