433659ad1e
While similar to the Bay Trail-M/D code based on the MRC, there are many differences as well: - Obviously, uses the FSP instead of the MRC binaries. - FSP does additional hardware setup, so coreboot doesn't need to. - Different microcode & microcode loading method - Uses the cache_as_ram.inc from the FSP Driver - Various other changes in support of the FSP Additional changes that don't have to to with the FSP vs MRC: - Updated IRQ Routing - Different FADT implementation. This was validated with FSP: BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5 MD5: 9360cd915f0d3e4116bbc782233d7b91 Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5791 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
116 lines
3.3 KiB
C
116 lines
3.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <baytrail/pci_devs.h>
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#include <baytrail/ramstage.h>
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#include <drivers/intel/fsp/fsp_util.h>
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#include "chip.h"
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static void pci_domain_set_resources(device_t dev)
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{
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assign_resources(dev->link_list);
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}
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static void finalize_dev (device_t dev)
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{
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/*
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* Notify FSP for PostPciEnumeration.
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* Northbridge APIC init should be early and late enough...
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*/
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printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
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FspNotify(EnumInitPhaseAfterPciEnumeration);
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = NULL,
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.init = NULL,
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.final = &finalize_dev,
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.scan_bus = pci_domain_scan_bus,
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.ops_pci_bus = pci_bus_default_ops,
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};
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static void cpu_bus_noop(device_t dev) { }
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static struct device_operations cpu_bus_ops = {
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.read_resources = cpu_bus_noop,
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.set_resources = cpu_bus_noop,
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.enable_resources = cpu_bus_noop,
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.init = baytrail_init_cpus,
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.scan_bus = NULL,
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};
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static void enable_dev(device_t dev)
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{
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printk(BIOS_DEBUG, "enable_dev(%s, %d)\n",
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dev_name(dev), dev->path.type);
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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dev->ops = &pci_domain_ops;
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} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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} else if (dev->path.type == DEVICE_PATH_PCI) {
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/* Handle south cluster enablement. */
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if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV &&
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(dev->ops == NULL || dev->ops->enable == NULL)) {
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southcluster_enable_dev(dev);
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}
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}
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}
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static void finalize_chip(void *chip_info)
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{
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/* Notify FSP for ReadyToBoot */
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printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n");
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FspNotify(EnumInitPhaseReadyToBoot);
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}
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/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */
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static void soc_init(void *chip_info)
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{
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baytrail_init_pre_device();
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}
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struct chip_operations soc_intel_fsp_baytrail_ops = {
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CHIP_NAME("Intel BayTrail SoC")
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.enable_dev = enable_dev,
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.init = soc_init,
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.final = &finalize_chip,
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};
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static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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pci_read_config32(dev, PCI_VENDOR_ID));
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} else {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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}
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struct pci_operations soc_pci_ops = {
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.set_subsystem = &pci_set_subsystem,
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};
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