This file isn't correct, since the Stoneyridge SoC doesn't have a legacy
PCI bridge on bus 0 bridge 0x14 function 4. Google/Kahlee doesn't select
HAVE_PIRQ_TABLE, so it's likely safe to also not select it for this
board.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibaf470b9ff7823019772d43af98ebc47af395728
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
badea79500