1abeef6005
There needs to be an ACPI linkage to provide the power resource needed to wake this device so the kernel will enable the SCI before going to suspend. A link is added for both NIC and WLAN, but it is only tested on the NIC. This is a forward port from Duncan's beltino patch. BUG=chrome-os-partner:24657 BRANCH=panther TEST=build and boot on panther, suspend and wake with etherwake Change-Id: I2804d2e904e26d6e34f5a177f0dabc1aaa3f0288 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181752 Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/5998 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
64 lines
1.7 KiB
Text
64 lines
1.7 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2012 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define ENABLE_TPM
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20110725 // OEM revision
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)
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{
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// Some generic macros
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#include "acpi/platform.asl"
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// global NVS and variables
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#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
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// General Purpose Events
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//#include "acpi/gpe.asl"
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// CPU
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#include <cpu/intel/haswell/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <northbridge/intel/haswell/acpi/haswell.asl>
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#include <southbridge/intel/lynxpoint/acpi/pch.asl>
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}
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}
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// Mainboard devices
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#include "acpi/mainboard.asl"
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// Thermal handler
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#include "acpi/thermal.asl"
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// Chrome OS specific
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#include "acpi/chromeos.asl"
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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// Chipset specific sleep states
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#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
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}
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