a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
91 lines
3.1 KiB
Text
91 lines
3.1 KiB
Text
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2013 Advanced Micro Devices, Inc.
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# Copyright (C) 2014 Sage Electronic Engineering, LLC
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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chip northbridge/amd/agesa/family16kb/root_complex
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device cpu_cluster 0 on
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chip cpu/amd/agesa/family16kb
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device lapic 0 on end
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end
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end
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device domain 0 on
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subsystemid 0x1022 0x1410 inherit
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chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
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chip northbridge/amd/agesa/family16kb # PCI side of HT root complex
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device pci 0.0 on end # Root Complex
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device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
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device pci 1.1 on end # Internal Multimedia
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device pci 2.0 on end # PCIe Host Bridge
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device pci 2.1 off end # unused
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device pci 2.2 on end # GPP0: NIC
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device pci 2.3 on end # GPP1: NIC
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device pci 2.4 off end # GPP2: unused
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device pci 2.5 off end # GPP3: unused
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end #chip northbridge/amd/agesa/family16kb
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chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
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device pci 11.0 on end # SATA
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device pci 12.0 on end # USB
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device pci 12.2 on end # USB
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device pci 13.0 on end # USB
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device pci 13.2 on end # USB
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device pci 14.0 on # SM
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chip drivers/generic/generic #dimm 0-0-0
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device i2c 50 on end
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end
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end # SM
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device pci 14.2 off end # HDA 0x4383
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device pci 14.3 on # LPC 0x439d
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chip superio/nuvoton/nct5104d
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device pnp 4e.0 off end # FDC
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device pnp 4e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.3 on # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 4e.7 off end # GPIO
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device pnp 4e.8 off end # GPIO/WDT
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device pnp 4e.f off end # GPIO
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device pnp 4e.10 off end # COM3 used by port 80
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device pnp 4e.11 on # COM4
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io 0x60 = 0x2e8
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irq 0x70 = 3
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end
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device pnp 4e.14 off end # PORT80
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register "irq_trigger_type" = "0" # 0 edge, 1 level
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end # nct5104d
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end #LPC
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device pci 14.7 off end # SD
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device pci 16.0 on end # USB
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device pci 16.2 on end # USB
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end #chip southbridge/amd/hudson
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device pci 18.0 on end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.5 on end
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register "spdAddrLookup" = "
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{
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{ {0xA0, 0x00}, {0x00, 0x00}, }, // socket 0 - Channel 0 - 8-bit SPD addresses
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}"
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end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
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end #domain
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end #northbridge/amd/agesa/family16kb/root_complex
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