coreboot-kgpe-d16/src
Kyösti Mälkki 4663f45caa device/pci_ops: Have only default PCI bus ops available
In the current state of the tree we do not utilise the
mechanism of having per-device overrides for PCI bus
ops.

This change effectively inlines all PCI config accessors
for ramstage as well.

Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-16 15:19:33 +00:00
..
acpi
arch device/pci_ops: Have only default PCI bus ops available 2019-03-16 15:19:33 +00:00
commonlib src: Drop unused '#include <halt.h>' 2019-03-16 11:46:58 +00:00
console coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
cpu src: Drop unused '#include <halt.h>' 2019-03-16 11:46:58 +00:00
device device/pci_ops: Have only default PCI bus ops available 2019-03-16 15:19:33 +00:00
drivers drivers/intel/fsp1_0: Deduplicate code 2019-03-16 09:01:50 +00:00
ec src: Drop unused '#include <halt.h>' 2019-03-16 11:46:58 +00:00
include device/pci_ops: Have only default PCI bus ops available 2019-03-16 15:19:33 +00:00
lib Remove leftover files 2019-03-14 11:32:06 +00:00
mainboard src: Drop unused '#include <halt.h>' 2019-03-16 11:46:58 +00:00
northbridge src: Drop unused '#include <halt.h>' 2019-03-16 11:46:58 +00:00
security vboot: rename symbols for better consistency 2019-03-15 12:59:29 +00:00
soc src: Drop unused '#include <halt.h>' 2019-03-16 11:46:58 +00:00
southbridge src: Drop unused '#include <halt.h>' 2019-03-16 11:46:58 +00:00
superio Remove leftover files 2019-03-14 11:32:06 +00:00
vendorcode vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake 2019-03-15 12:47:30 +00:00
Kconfig