5e83e8b130
Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp. TODO: Fix as per octopus schematic. Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23685 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
62 lines
1.7 KiB
C
62 lines
1.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec.h>
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#include <intelblocks/lpc_lib.h>
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#include <rules.h>
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#include <variant/ec.h>
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static void ramstage_ec_init(void)
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{
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static const struct google_chromeec_event_info info = {
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.log_events = MAINBOARD_EC_LOG_EVENTS,
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.sci_events = MAINBOARD_EC_SCI_EVENTS,
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.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
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.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
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.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
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};
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printk(BIOS_ERR, "mainboard: EC init\n");
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google_chromeec_events_init(&info, acpi_is_wakeup_s3());
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}
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static void bootblock_ec_init(void)
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{
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uint16_t ec_ioport_base;
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size_t ec_ioport_size;
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/*
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* Set up LPC decoding for the ChromeEC I/O port ranges:
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* - Ports 62/66, 60/64, and 200->208
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* - ChromeEC specific communication I/O ports.
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*/
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lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64
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| LPC_IOE_LGE_200);
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google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
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lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
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}
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void mainboard_ec_init(void)
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{
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if (ENV_RAMSTAGE)
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ramstage_ec_init();
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else if (ENV_BOOTBLOCK)
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bootblock_ec_init();
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}
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