8e079000dc
This reuses some of gm45 code to set up the panel. Panel start and stop delays and pwm frequency can now be set in devicetree. Linux does not make the difference between 945gm and gm45 for panel delays, so it is safe to assume the semantics of those registers are the same. The core display clock is computed according to "Mobile Intel® 945 Express Chipset Family" Datasheet. This selects Legacy backlight mode since most targets have some smm code that rely on this. This sets the same backlight frequency as vendor bios on Thinkpad X60 and T60. A default of 180Hz is selected for the PWM frequency if it is not defined in the devicetree, this might be annoying for displays that are LED backlit, but is a safe value for CCFL backlit displays. Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18141 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
225 lines
5.7 KiB
Text
225 lines
5.7 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2009 coresystems GmbH
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## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip northbridge/intel/i945
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# IGD Displays
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register "gfx.ndid" = "3"
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
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register "gpu_hotplug" = "0x00000220"
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register "gpu_lvds_use_spread_spectrum_clock" = "1"
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register "pwm_freq" = "180"
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register "gpu_panel_power_up_delay" = "250"
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register "gpu_panel_power_backlight_on_delay" = "2380"
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register "gpu_panel_power_down_delay" = "250"
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register "gpu_panel_power_backlight_off_delay" = "2380"
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register "gpu_panel_power_cycle_delay" = "2"
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device cpu_cluster 0 on
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chip cpu/intel/socket_mFCPGA478
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device lapic 0 on end
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end
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end
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register "pci_mmio_size" = "768"
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device domain 0 on
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device pci 00.0 on # Host bridge
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subsystemid 0x17aa 0x2017
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end
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device pci 02.0 on # VGA controller
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subsystemid 0x17aa 0x201a
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end
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device pci 02.1 on # display controller
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subsystemid 0x17aa 0x201a
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end
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chip southbridge/intel/i82801gx
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register "pirqa_routing" = "0x0b"
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register "pirqb_routing" = "0x0b"
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register "pirqc_routing" = "0x0b"
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register "pirqd_routing" = "0x0b"
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register "pirqe_routing" = "0x0b"
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register "pirqf_routing" = "0x0b"
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register "pirqg_routing" = "0x0b"
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register "pirqh_routing" = "0x0b"
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "gpi13_routing" = "2"
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register "gpi12_routing" = "1"
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register "gpi8_routing" = "2"
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register "sata_ahci" = "0x1"
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register "sata_ports_implemented" = "0x01"
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register "gpe0_en" = "0x11000006"
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register "alt_gp_smi_en" = "0x1000"
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register "c4onc3_enable" = "1"
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register "c3_latency" = "0x23"
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register "docking_supported" = "1"
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register "p_cnt_throttling_supported" = "1"
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device pci 1b.0 on # Audio Controller
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subsystemid 0x17aa 0x2010
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end
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device pci 1c.0 on end # Ethernet
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device pci 1c.1 on end # Atheros WLAN
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device pci 1d.0 on # USB UHCI
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subsystemid 0x17aa 0x200a
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end
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device pci 1d.1 on # USB UHCI
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subsystemid 0x17aa 0x200a
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end
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device pci 1d.2 on # USB UHCI
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subsystemid 0x17aa 0x200a
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end
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device pci 1d.3 on # USB UHCI
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subsystemid 0x17aa 0x200a
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end
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device pci 1d.7 on # USB2 EHCI
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subsystemid 0x17aa 0x200b
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end
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device pci 1f.0 on # PCI-LPC bridge
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subsystemid 0x17aa 0x2009
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chip ec/lenovo/pmh7
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device pnp ff.1 on # dummy
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end
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register "backlight_enable" = "0x01"
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register "dock_event_enable" = "0x01"
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end
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chip ec/lenovo/h8
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device pnp ff.2 on # dummy
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io 0x60 = 0x62
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io 0x62 = 0x66
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io 0x64 = 0x1600
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io 0x66 = 0x1604
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end
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register "config0" = "0xa6"
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register "config1" = "0x05"
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register "config2" = "0xa0"
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register "config3" = "0x01"
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register "beepmask0" = "0xfe"
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register "beepmask1" = "0x96"
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register "has_power_management_beeps" = "1"
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register "event2_enable" = "0xff"
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register "event3_enable" = "0xff"
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register "event4_enable" = "0xf4"
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register "event5_enable" = "0x3c"
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register "event6_enable" = "0x80"
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register "event7_enable" = "0x01"
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register "event8_enable" = "0x01"
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register "event9_enable" = "0xff"
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register "eventa_enable" = "0xff"
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register "eventb_enable" = "0xff"
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register "eventc_enable" = "0xff"
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register "eventd_enable" = "0xff"
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end
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chip superio/nsc/pc87382
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device pnp 164e.2 on # IR
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io 0x60 = 0x2f8
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end
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device pnp 164e.3 on # Digitizer
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io 0x60 = 0x200
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irq 0x29 = 0xb0
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irq 0x70 = 0x5
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irq 0xf0 = 0x82
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end
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device pnp 164e.7 on # GPIO
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io 0x60 = 0x1680
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end
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device pnp 164e.19 on # DLPC
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io 0x60 = 0x164c
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end
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end
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chip superio/nsc/pc87392
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device pnp 2e.0 off #FDC
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end
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device pnp 2e.1 on # Parallel Port
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io 0x60 = 0x3bc
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irq 0x70 = 7
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end
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device pnp 2e.2 off # Serial Port / IR
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io 0x60 = 0x2f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # Serial Port
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.7 on # GPIO
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io 0x60 = 0x1620
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end
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device pnp 2e.a off # WDT
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end
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end
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end
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device pci 1f.1 on # IDE
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subsystemid 0x17aa 0x200c
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end
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device pci 1f.2 on # SATA
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subsystemid 0x17aa 0x200d
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end
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device pci 1f.3 on # SMBUS
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subsystemid 0x17aa 0x200f
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chip drivers/ics/954309
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register "reg0" = "0x2e"
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register "reg1" = "0xf7"
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register "reg2" = "0x3c"
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register "reg3" = "0x20"
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register "reg4" = "0x01"
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register "reg5" = "0x00"
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register "reg6" = "0x1b"
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register "reg7" = "0x01"
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register "reg8" = "0x54"
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register "reg9" = "0xff"
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register "reg10" = "0xff"
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register "reg11" = "0x07"
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device i2c 69 on end
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end
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# eeprom, 8 virtual devices, same chip
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chip drivers/i2c/at24rf08c
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device i2c 54 on end
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device i2c 55 on end
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device i2c 56 on end
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device i2c 57 on end
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device i2c 5c on end
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device i2c 5d on end
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device i2c 5e on end
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device i2c 5f on end
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end
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end
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end
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chip southbridge/ricoh/rl5c476
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end
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end
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end
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