coreboot-kgpe-d16/src/arch
Deepa Dinamani 47722957a1 arch: armv7: Fix cache sync instructions.
When the i-cache is on and the d-cache is off, the L1 i-cache is still
fetching information through L2 cache.
Since L2 cache is never invalidated, it has stale information.

BRANCH=storm
BUG=none
TEST=Resolves the invalidate data fetch from i-cache while jumping from
bootblock to romstage.

Change-Id: Ibaca1219be2e40ce5bbbd1c124863d0ea71d0466
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: a13e20f9b242d8193dcb314a2bdc708c6bdfea51
Original-Change-Id: I252682d372bd505f525f075461b327e4bcf70a1a
Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/236422
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9587
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13 12:19:11 +02:00
..
arm arch: armv7: Fix cache sync instructions. 2015-04-13 12:19:11 +02:00
arm64 arm64: No need of invalidating cache line for secondary CPU stack 2015-04-10 20:47:52 +02:00
mips timer: Add generic udelay() implementation 2015-04-08 18:35:01 +02:00
riscv kconfig: drop intermittend forwarder files 2015-04-07 17:40:28 +02:00
x86 x86: Support reset routines in bootblock 2015-04-10 20:28:45 +02:00