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Aaron Durbin 1936f6cf25 timestamp: add generic cache region 
In order to accommodate tracking timestamps in all the
__PRE_RAM__ stages (bootblock, verstage, romstage, etc)
of a platform one needs to provide a way to specify
a persistent region of SRAM or cache-as-ram to store
the timestamps until cbmem comes online. Provide that
infrastructure.

Based on original patches from chromium.org:
Original-Change-Id: I4d78653c0595523eeeb02115423e7fecceea5e1e
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/223348
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>

Original-Change-Id: Ie5ffda3112d626068bd1904afcc5a09bc4916d16
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/224024
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>

Change-Id: I8779526136e89ae61a6f177ce5c74a6530469ae1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10790
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-07-07 20:07:27 +02:00
..
bootblock_normal.c Replace hlt with halt() 2014-12-02 10:25:55 +01:00
bootblock_simple.c Replace hlt with halt() 2014-12-02 10:25:55 +01:00
crt0_romcc_epilogue.inc Remove empty lines at end of file 2015-06-08 00:55:07 +02:00
failover.ld x86: Move architecture selection from linker script to Makefile.inc 2015-06-26 22:44:10 +02:00
Makefile.inc
prologue.inc Remove empty lines at end of file 2015-06-08 00:55:07 +02:00
romstage.ld timestamp: add generic cache region 2015-07-07 20:07:27 +02:00