00809ebf02
targets/*/*/Makefile
targets/*/*/normal/Makefile
targets/*/*/fallback/Makefile
to use a common copy of romcc, and to leave this compiler untouched by
'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ .
'make clean' in targets/*/*/ will clean romcc.
Thanks to Mats for the initial idea and implementation of a tool to do
this. This patch has almost the same behaviour as the original tool
without having to run the tool each time.
Tested for abuild-friendliness.
The patch saves ~10-12 seconds for every target using romcc. For a full
abuild run, this is ~20% time saved.
For the first 38 abuild targets, total build time is down to 13m24s
instead of 16m22s on my machine.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
213 lines
5.2 KiB
Text
213 lines
5.2 KiB
Text
##
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## Only use the option table in a normal image
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##
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default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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##
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## Compute the location and size of where this firmware image
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## (coreboot plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The coreboot bootloader.
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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##
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## Compute where this copy of coreboot will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up coreboot,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=131072
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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object reset.o
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c ../romcc"
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action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/failover.c ../romcc"
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action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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##
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## Build our 16 bit and 32 bit coreboot entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where coreboot is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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### This is the early phase of coreboot startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit cpu/x86/sse/enable_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/sse/disable_sse.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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chip northbridge/intel/e7520
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device pci_domain 0 on
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device pci 00.0 on end
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device pci 00.1 on end
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device pci 01.0 on end
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device pci 02.0 on
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chip southbridge/intel/pxhd # pxhd1
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device pci 00.0 on end
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device pci 00.1 on end
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device pci 00.2 on
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chip drivers/generic/generic
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device pci 04.0 on end
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device pci 04.1 on end
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end
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end
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device pci 00.3 on end
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end
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end
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device pci 06.0 on end
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chip southbridge/intel/i82801er # i82801er
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device pci 1d.0 on end
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device pci 1d.1 on end
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device pci 1d.2 on end
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device pci 1d.3 off end
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device pci 1d.7 on end
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device pci 1e.0 on
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chip drivers/ati/ragexl
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device pci 0c.0 on end
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end
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end
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device pci 1f.0 on
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chip superio/nsc/pc87427
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device pnp 2e.0 off end
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device pnp 2e.2 on
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# io 0x60 = 0x2f8
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# irq 0x70 = 3
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on
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# io 0x60 = 0x3f8
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# irq 0x70 = 4
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.4 off end
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device pnp 2e.5 off end
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device pnp 2e.6 on
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.7 off end
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device pnp 2e.9 off end
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device pnp 2e.a off end
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device pnp 2e.f on end
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device pnp 2e.10 off end
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device pnp 2e.14 off end
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end
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end
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device pci 1f.1 on end
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device pci 1f.2 off end
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device pci 1f.3 on end
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device pci 1f.5 off end
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device pci 1f.6 off end
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register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO"
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register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW"
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register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT"
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end
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end
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device apic_cluster 0 on
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chip cpu/intel/socket_mPGA604_800Mhz # cpu 0
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device apic 0 on end
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end
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chip cpu/intel/socket_mPGA604_800Mhz # cpu 1
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device apic 6 on end
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end
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end
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end
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