486c05f4bf
A set of pins can be configured for GPIO or (parallel) PCI bridge use. When requested configuration is 0:14.4 enabled, register programming must be done before attempting to enumerate devices behind the bridge. When requested configuration is 0:14.4 disabled, we must not even temporarily enable pins for PCI use to avoid spurious GPIO state changes. As our PCI subsystem currently does not configure visible PCI bridges that are marked disabled, we cannot mark 0:14.4 disabled just yet but need to handle pcengines/apu1 as a special case. Drop related dead code. Change-Id: I8644ebae43b33121ef2a7ed30f745299716ce0df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8329 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> |
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| .. | ||
| acpi | ||
| acpi_tables.c | ||
| board_info.txt | ||
| cmos.layout | ||
| devicetree.cb | ||
| dsdt.asl | ||
| get_bus_conf.c | ||
| irq_tables.c | ||
| Kconfig | ||
| mainboard.c | ||
| Makefile.inc | ||
| mb_sysconf.h | ||
| mptable.c | ||
| platform_cfg.h | ||
| resourcemap.c | ||
| romstage.c | ||