260 lines
6.9 KiB
C
260 lines
6.9 KiB
C
/*
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* This file is part of msrtool.
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*
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* Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "msrtool.h"
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int intel_pentium3_early_probe(const struct targetdef *target, const struct cpuid_t *id) {
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return ((0x6 == id->family) && (
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(0x7 == id->model) ||
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(0x8 == id->model)
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));
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}
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const struct msrdef intel_pentium3_early_msrs[] = {
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{0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", {
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{ BITS_EOT }
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}},
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{0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", {
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{ BITS_EOT }
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}},
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{0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
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{ BITS_EOT }
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}},
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{0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
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{ BITS_EOT }
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}},
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{0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
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{ BITS_EOT }
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}},
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{0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", {
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{ BITS_EOT }
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}},
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{0x33, MSRTYPE_RDWR, MSR2(0,0), "TEST_CTL", "", {
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{ BITS_EOT }
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}},
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{0x88, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D0", "", {
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{ BITS_EOT }
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}},
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{0x89, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D1", "", {
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{ BITS_EOT }
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}},
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{0x8a, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D2", "", {
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{ BITS_EOT }
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}},
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{0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
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{ BITS_EOT }
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}},
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{0xc1, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR0", "", {
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{ BITS_EOT }
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}},
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{0xc2, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR1", "", {
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{ BITS_EOT }
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}},
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{0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
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{ BITS_EOT }
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}},
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{0x116, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_ADDR", "", {
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{ BITS_EOT }
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}},
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{0x118, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_DECC", "", {
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{ BITS_EOT }
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}},
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{0x119, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL", "", {
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{ BITS_EOT }
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}},
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{0x11b, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_BUSY", "", {
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{ BITS_EOT }
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}},
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{0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", {
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{ BITS_EOT }
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}},
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{0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", {
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{ BITS_EOT }
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}},
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{0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", {
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{ BITS_EOT }
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}},
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{0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", {
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{ BITS_EOT }
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}},
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{0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
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{ BITS_EOT }
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}},
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{0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
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{ BITS_EOT }
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}},
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{0x17b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CTL", "", {
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{ BITS_EOT }
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}},
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{0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_EVNTSEL0", "", {
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{ BITS_EOT }
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}},
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{0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_EVNTSEL1", "", {
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{ BITS_EOT }
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}},
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{0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
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{ BITS_EOT }
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}},
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{0x1db, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCHFROMIP", "", {
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{ BITS_EOT }
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}},
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{0x1dc, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCHTOIP", "", {
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{ BITS_EOT }
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}},
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{0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTINTFROMIP", "", {
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{ BITS_EOT }
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}},
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{0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTINTTOIP", "", {
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{ BITS_EOT }
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}},
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{0x1e0, MSRTYPE_RDWR, MSR2(0,0), "MSR_ROB_CR_BKUPTMPDR6", "", {
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{ BITS_EOT }
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}},
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{0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
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{ BITS_EOT }
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}},
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{0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
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{ BITS_EOT }
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}},
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{0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
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{ BITS_EOT }
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}},
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{0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
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{ BITS_EOT }
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}},
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{0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
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{ BITS_EOT }
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}},
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{0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
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{ BITS_EOT }
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}},
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{0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
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{ BITS_EOT }
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}},
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{0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
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{ BITS_EOT }
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}},
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{0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
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{ BITS_EOT }
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}},
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{0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
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{ BITS_EOT }
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}},
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{0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
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{ BITS_EOT }
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}},
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{0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
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{ BITS_EOT }
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}},
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{0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
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{ BITS_EOT }
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}},
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{0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
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{ BITS_EOT }
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}},
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{0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
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{ BITS_EOT }
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}},
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{0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
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{ BITS_EOT }
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}},
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{0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
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{ BITS_EOT }
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}},
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{0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
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{ BITS_EOT }
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}},
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{0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
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{ BITS_EOT }
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}},
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{0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
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{ BITS_EOT }
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}},
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{0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
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{ BITS_EOT }
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}},
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{0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
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{ BITS_EOT }
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}},
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{0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
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{ BITS_EOT }
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}},
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{0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
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{ BITS_EOT }
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}},
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{0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
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{ BITS_EOT }
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}},
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{0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
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{ BITS_EOT }
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}},
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{0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
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{ BITS_EOT }
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}},
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{0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
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{ BITS_EOT }
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}},
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{0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
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{ BITS_EOT }
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}},
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{0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
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{ BITS_EOT }
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}},
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{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
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{ BITS_EOT }
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}},
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{0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", {
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{ BITS_EOT }
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}},
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{0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", {
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{ BITS_EOT }
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}},
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{0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", {
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{ BITS_EOT }
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}},
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{0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", {
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{ BITS_EOT }
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}},
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{0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", {
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{ BITS_EOT }
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}},
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{0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
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{ BITS_EOT }
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}},
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{0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
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{ BITS_EOT }
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}},
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{0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
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{ BITS_EOT }
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}},
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{0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
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{ BITS_EOT }
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}},
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{0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
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{ BITS_EOT }
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}},
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{0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
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{ BITS_EOT }
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}},
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{0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
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{ BITS_EOT }
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}},
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{ MSR_EOT }
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};
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