Matt Papageorge b87effe1dd soc/amd/picasso/romstage: Set SATA enable UPD if controller is enabled ... FSP has recently added support for a UPD switch to power gate SATA. This change adds the coreboot side of the feature. To avoid having two SATA enable options, the value of the sata_enable UPD is determined by the enable state of the AHCI controller in the platform devicetree. BUG=b:162302027 BRANCH=zork TEST=Verify AHCI controller can be hidden/disabled. Change-Id: I48bf94a7e6249db6079a6e3de7456a536d54a242 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44067 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-08-28 17:50:50 +00:00
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amd	soc/amd/picasso/romstage: Set SATA enable UPD if controller is enabled	2020-08-28 17:50:50 +00:00
cavium	symbols: Change implementation details of DECLARE_OPTIONAL_REGION()	2020-08-27 22:11:17 +00:00
intel	vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt soc	2020-08-28 17:44:46 +00:00
mediatek	soc/mediatek/mt8192: Use SPI-NOR as flash controller	2020-08-28 04:44:56 +00:00
nvidia	src: Remove unused 'include <stddef.h>	2020-08-18 12:15:44 +00:00
qualcomm	src: Remove unused 'include <delay.h>'	2020-08-18 12:19:18 +00:00
rockchip	src/soc/rockchip: Add missing <{stddef,stdint}.h>	2020-07-29 09:37:22 +00:00
samsung	src/soc/samsung/exynos{5250,s5420}: Add missing <{stddef,stdint}.h>	2020-07-29 09:34:55 +00:00
sifive	soc/sifive: Drop unneeded empty lines	2020-08-24 09:16:48 +00:00
ti	cpu/ti/am335x: Move from cpu to soc in tree	2020-08-19 07:17:37 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00