Matt Delco 4988fe2986 src/include: add more msr defines ... This change adds some MSRs that are needed in a subsequent change to add support for Continuous Performance Control. Change-Id: Id4ecff1bc5eedaa90b41de526b9a2e61992ac296 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>		2018-08-17 20:13:21 +00:00
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bist.h	x86 BIST: Fix missing include	2016-11-24 21:39:41 +01:00
cache.h	include/cpu/x86: Add clflush inline function	2017-12-20 16:36:43 +00:00
cr.h	arch/x86: print cr2 value on every exception	2018-04-26 15:18:41 +00:00
gdt.h	tree: drop last paragraph of GPL copyright header	2015-10-31 21:37:39 +01:00
lapic.h	arch/x86: Fix ugly NEED_LAPIC use	2017-08-19 15:30:40 +00:00
lapic_def.h	src/include: Remove spaces before tabs	2017-03-12 15:45:37 +01:00
mp.h	cpu/x86: Add support to run function on single AP	2018-05-19 01:16:06 +00:00
msr.h	src/include: add more msr defines	2018-08-17 20:13:21 +00:00
mtrr.h	cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x	2018-07-30 19:03:27 +00:00
name.h	tree: drop last paragraph of GPL copyright header	2015-10-31 21:37:39 +01:00
pae.h	cpu/x86: add limited runtime identity page mapping	2018-04-26 06:55:59 +00:00
post_code.h	src/include: Add guards on all header files	2017-08-01 23:04:15 +00:00
smm.h	smm: Add canary to end of stack and die() if a stack overflow occurs	2018-06-28 09:01:02 +00:00
tsc.h	nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xce	2018-06-14 10:00:03 +00:00